Florent Kermarrec
|
51c5d69586
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targets/tec0117: use custom CPU/ROM/SRAM config to minimize resources.
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2021-02-01 13:31:56 +01:00 |
|
Florent Kermarrec
|
538878ce13
|
tec0117: disable BIOS XIP from SPI Flash for now since not working (SPÏ Flash set to power down mode with bitstream?).
|
2021-02-01 13:31:51 +01:00 |
|
Florent Kermarrec
|
6cce07d9db
|
tec0117: add spiflash4x pins, rework flash function to flash both bitstream/bios.
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2021-02-01 13:31:44 +01:00 |
|
Florent Kermarrec
|
0831b33285
|
tec0117: fix copyrights.
|
2021-02-01 13:31:39 +01:00 |
|
Florent Kermarrec
|
abccd12058
|
tec0117: add initial SDRAM support for the embedded SDRAM of the SIP.
Still a WIP but able to do the P&R with modifications on LiteX to generate
the IO_PORT constraints but not the IO_LOC for the SDRAM pins.
|
2021-01-29 22:28:40 +01:00 |
|
Florent Kermarrec
|
edb99797aa
|
targets/tec0117: minor cleanups.
|
2021-01-29 21:25:10 +01:00 |
|
Florent Kermarrec
|
d42af3ea19
|
targets: add --sys-clk-freq support to all targets.
|
2020-11-12 18:07:28 +01:00 |
|
Florent Kermarrec
|
bd4e92ad13
|
targets: cleanup, uniformize build arguments between targets.
|
2020-11-12 11:46:00 +01:00 |
|
Florent Kermarrec
|
2b17dc1b89
|
target: add rst signal to CRG to allow full reset of the SoC on reboot command.
|
2020-11-04 11:13:42 +01:00 |
|
Florent Kermarrec
|
ce14775dfb
|
targets/tec0117: move SerialFlashManager import to flash function.
|
2020-11-04 09:30:31 +01:00 |
Pepijn de Vos
|
18e5def9f2
|
don't verify erase, very slow
|
2020-10-01 08:41:16 +02:00 |
|
Pepijn de Vos
|
81e4f1f158
|
add initial support for Trenz TEC0117 board
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2020-09-30 14:01:36 +02:00 |