litex-boards

Commit Graph

Author	SHA1	Message	Date
Florent Kermarrec	d73bd2f7ce	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
Florent Kermarrec	1ac1c6857f	targets/xilinx: add false path constraint between sys_clk and pll.clkin. The SoC reset added recently creates a path between sys_clk and pll.clkin clock domains that is reported by the tools but that can be safely ignored.	2021-01-07 00:02:46 +01:00
Nathaniel R. Lewis	389b623fe2	targets/litefury: new target LiteFury is an Artix-7 development board in the M.2 form factor for PCIe accelerator development. It's similar to the Aller but with an xc7a100t rather than an xc7a200t and no TPM module. https://rhsresearch.com/collections/rhs-public/products/litefury	2020-11-19 21:52:14 -08:00

Author

SHA1

Message

Date

Florent Kermarrec

d73bd2f7ce

targets/xilinx: add comment on sys_clk to pll.clkin false path.

2021-01-07 08:01:54 +01:00

Florent Kermarrec

1ac1c6857f

targets/xilinx: add false path constraint between sys_clk and pll.clkin.

The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.

2021-01-07 00:02:46 +01:00

Nathaniel R. Lewis

389b623fe2

targets/litefury: new target

LiteFury is an Artix-7 development board in the M.2 form factor
for PCIe accelerator development. It's similar to the Aller but
with an xc7a100t rather than an xc7a200t and no TPM module.

https://rhsresearch.com/collections/rhs-public/products/litefury

2020-11-19 21:52:14 -08:00

3 Commits