4 Commits

Author	SHA1	Message	Date
Arnaud Durand	618f41bb1e	Update ecp5_evn.py ... The system clock was driven directly while it should be driven by the PLL.	2019-08-22 02:27:50 +02:00
DurandA	c90950e319	Default to 60 Mhz system clock on ECP5 Evaluation Board ... Exact PLL clock can be derived from U1 12 Mhz or X5 50 Mhz clock.	2019-08-09 11:58:30 +02:00
DurandA	4126ed21d5	Add X5 clock and PLL to ECP5 Evaluation Board	2019-08-09 11:54:38 +02:00
DurandA	c7444fe19c	Add ECP5 Evaluation Board	2019-08-09 09:45:13 +02:00