Commit Graph

12 Commits

Author SHA1 Message Date
Florent Kermarrec c093d0d0fc platforms: cleanup pass to uniformize comments/separators/orders. 2020-11-03 10:48:57 +01:00
Florent Kermarrec 1781be166a general: add SPDX License identifier to header and specify files are part of LiteX-Boards. 2020-08-23 15:00:17 +02:00
Florent Kermarrec 1f88a9d5ec platforms: make sure clocks inputs are constraints on all platforms.
Also use new loose lookup_request to simplify constraints.
2020-05-05 11:45:41 +02:00
Florent Kermarrec 86648ec7d8 platforms/vcu118: rename ddram_second_channel to ddram:1. 2020-05-05 09:54:11 +02:00
Florent Kermarrec 2cf3c3e845 platforms: cosmetic cleanups. 2020-04-09 23:05:13 +02:00
Florent Kermarrec 95e1a05bf1 platforms/Ultrascale: avoid unnecessary {{}} on INTERNAL_VREF. 2020-03-09 09:29:49 +01:00
Florent Kermarrec d4460c11a5 platforms/kcu105/vcu118: remove PRE_EMPHASIS/EQUALIZATION on dm. 2020-02-27 10:43:41 +01:00
Florent Kermarrec e516ff3452 vcu118/ddram: use similar IO settings than Xilinx's MIG, comment unused pins. 2020-02-26 10:16:51 +01:00
Florent Kermarrec 83d2c71099 platforms/vcu118: add missing Internal Vref configuration on DDR4 C1/C2 banks 2020-02-25 18:32:42 +01:00
Florent Kermarrec f279fe9d33 vc707: cleanup platform/targets, remove Ethernet support (no Ethernet pads defined) 2020-02-25 10:35:18 +01:00
Florent Kermarrec 88a1f80db1 vc707/vcu118: use proper copyrights 2020-02-25 09:03:52 +01:00
Fei Gao 373e74f435 add new board files for VC707 and VCU118, only specified limited ports for VCU118, including clock, reset and DDR4 2020-02-24 14:20:47 -05:00