4 commits

Author	SHA1	Message	Date
Florent Kermarrec	a611f035d6	targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible. ... Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical. Also do some minor updates/cosmetic changes while touching CRG/SoCCore.	2022-04-21 12:19:45 +02:00
Florent Kermarrec	00ff61baa9	targets: Simplify clock domains and remove useless reset_less. ... rst was not directly assigned/used on reset_less clock domains, so reset_less property was not really useful. With the changes on stream.CDC, having a rst (Even fixed at 0) is now mandatory on clock domains involved in the CDC, so this also fixes targets.	2022-04-01 11:30:38 +02:00
John Simons	901942bda6	Cleanup for pushing. This commit combined with my litedram fork produces a running basic SoC + bios --=============== SoC ==================-- ... CPU:BUS:E 32-bit @ 4GiB CSR:16-bit @ 48MT/s (CL-2 CWL-2) --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Switching SDRAM to hardware control. Memtest at 0x40000000 (2.0MiB)... Write: 0x40000000-0x40200000 2.0MiB Read: 0x40000000-0x40200000 2.0MiB Memtest OK Memspeed at 0x40000000 (Sequential, 2.0MiB)... Write speed: 13.6MiB/s Read speed: 21.3MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely.	2022-03-24 07:39:14 -07:00
John Simons	b8b0aead28	Added basic support for Arduino MKR Vidor 4000	2022-03-21 18:54:29 -07:00