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8 Commits

Author SHA1 Message Date
Sylvain Munaut 24db5783c1 adi_adrv2crr: Fix typo in PMOD pinout 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2024-04-10 14:06:47 +02:00
Florent Kermarrec 47659835b0 platforms: Switch US/USP platforms to XilinxUS/USPPlatform. 
We were still using Xilinx7SeriesPlatform.
 2023-03-01 09:37:55 +01:00
Gwenhael Goavec-Merou 9960f38d95 targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser 2022-11-06 11:27:47 +01:00
Sylvain Munaut bcedf573e0 adi_adrv2crr: Add IO definition for the AD9545 reset line 
We use PULLUP on it so that the AD9545 is by default held out
of reset without the user having to do anything ...

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2022-03-23 20:42:30 +01:00
Sylvain Munaut cdb78efd3c adi_adrv2crr: Document I2C devices attached 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2022-03-23 20:42:30 +01:00
Sylvain Munaut 6c31f16df2 adi_adrv2crr: Fix I2C signal assignement 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2022-03-23 20:42:30 +01:00
Sylvain Munaut dc92584681 adi_adrv2crr: Upgrade part to speedgrade 2 
Even though the schematic and bom call for speedgrade 1, this was only for
the prototypes.

All productions units have been updated to speedgrade 2.

See this thread:
https://ez.analog.com/fpga/f/q-a/112356/adrv9009-zu11eg-speed-grade

And the official HDL project for the board:
https://github.com/analogdevicesinc/hdl/blob/master/projects/adrv9009zu11eg/adrv2crr_fmc/system_project.tcl#L16

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2022-03-22 23:36:41 +01:00
Sylvain Munaut ec28ca8fa3 adi_adrv2crr: Add support for the ADI ADRV2CRR with ADRV9009-ZU11EG SoM 
This is a carrier board with a SoM mounted on it.
There is also an FMC connector that can accept another
AD-FMCOMMS8-EBZ to get two more ADRV9009 RFIC but support for
that is not added yet.

Note that the PCIe support requires :
 - Change the .xci in the litepcie to use the right Quad
 - Revert litex 3c34039b731b42e27e2ee6c8e399e5eb8f3a058f so the
   timing constrainst of litepcie apply correctly

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2022-03-03 22:17:09 +01:00