156 lines
6.0 KiB
Python
Executable File
156 lines
6.0 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Icenowy Zheng <icenowy@aosc.io>
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import *
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from litex.build.io import DDROutput
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from litex.soc.cores.clock.gowin_gw2a import GW2APLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.gpio import GPIOIn
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from litex.soc.cores.led import LedChaser, WS2812
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from litedram.modules import M12L64322A # FIXME: use the real model number
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from litedram.phy import GENSDRPHY
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from litex_boards.platforms import sipeed_tang_nano_20k
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_por = ClockDomain()
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# Clk
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clk27 = platform.request("clk27")
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk27)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.pll = pll = GW2APLL(devicename=platform.devicename, device=platform.device)
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self.comb += pll.reset.eq(~por_done)
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pll.register_clkin(clk27, 27e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=48e6,
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with_led_chaser = True,
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with_rgb_led = False,
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with_buttons = True,
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**kwargs):
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platform = sipeed_tang_nano_20k.Platform(toolchain="gowin")
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Nano 20K", **kwargs)
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# TODO: XTX SPI Flash
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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class SDRAMPads:
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def __init__(self):
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self.clk = platform.request("O_sdram_clk")
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self.cke = platform.request("O_sdram_cke")
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self.cs_n = platform.request("O_sdram_cs_n")
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self.cas_n = platform.request("O_sdram_cas_n")
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self.ras_n = platform.request("O_sdram_ras_n")
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self.we_n = platform.request("O_sdram_wen_n")
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self.dm = platform.request("O_sdram_dqm")
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self.a = platform.request("O_sdram_addr")
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self.ba = platform.request("O_sdram_ba")
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self.dq = platform.request("IO_sdram_dq")
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sdram_pads = SDRAMPads()
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self.specials += DDROutput(0, 1, sdram_pads.clk, ClockSignal("sys"))
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self.sdrphy = GENSDRPHY(sdram_pads, sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = M12L64322A(sys_clk_freq, "1:1"), # FIXME.
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l2_cache_size = 128,
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)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("led_n"),
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sys_clk_freq = sys_clk_freq
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)
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# RGB Led ----------------------------------------------------------------------------------
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if with_rgb_led:
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self.rgb_led = WS2812(
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pad = platform.request("rgb_led"),
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nleds = 1,
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sys_clk_freq = sys_clk_freq
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)
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self.bus.add_slave(name="rgb_led", slave=self.rgb_led.bus, region=SoCRegion(
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origin = 0x2000_0000,
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size = 4,
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))
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# Buttons ----------------------------------------------------------------------------------
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if with_buttons:
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self.buttons = GPIOIn(pads=~platform.request_all("btn"))
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=sipeed_tang_nano_20k.Platform, description="LiteX SoC on Tang Nano 20K.")
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parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.")
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parser.add_target_argument("--sys-clk-freq", default=48e6, type=float, help="System clock frequency.")
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sdopts = parser.target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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**parser.soc_argdict
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)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".fs"), external=True)
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if __name__ == "__main__":
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main()
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