mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
00ff61baa9
rst was not directly assigned/used on reset_less clock domains, so reset_less property was not really useful. With the changes on stream.CDC, having a rst (Even fixed at 0) is now mandatory on clock domains involved in the CDC, so this also fixes targets.
113 lines
4.5 KiB
Python
Executable file
113 lines
4.5 KiB
Python
Executable file
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 msloniewski <marcin.sloniewski@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import DDROutput
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from litex_boards.platforms import de10lite
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from litex.soc.cores.clock import Max10PLL
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoVGAPHY
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from litex.soc.cores.led import LedChaser
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from litedram.modules import IS42S16320
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from litedram.phy import GENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain()
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self.clock_domains.cd_vga = ClockDomain()
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# # #
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# Clk / Rst
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clk50 = platform.request("clk50")
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# PLL
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self.submodules.pll = pll = Max10PLL(speedgrade="-7")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_vga, 40e6)
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# SDRAM clock
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_video_terminal=False,
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**kwargs):
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platform = de10lite.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on DE10-Lite",
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = IS42S16320(sys_clk_freq, "1:1"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Video Terminal ---------------------------------------------------------------------------
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if with_video_terminal:
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self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on DE10-Lite")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
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target_group.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_video_terminal = args.with_video_terminal,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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