90 lines
3.6 KiB
Python
90 lines
3.6 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Derek Mulcahy <derekmulcahy@gmail.com>
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# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst - FIXME: A placeholder for an external clock
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("clk100", 0, Pins("H16"), IOStandard("LVCMOS33")),
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# Leds - FIXME: A placeholder for an external LED
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("user_led", 0, Pins("G14"), IOStandard("LVCMOS33")),
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# UART - FIXME: A placeholder for an external UART
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("serial", 0,
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Subsignal("tx", Pins("D19")),
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Subsignal("rx", Pins("D20")),
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IOStandard("LVCMOS33"),
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),
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# PS7
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("ps7_clk", 0, Pins(1)),
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("ps7_porb", 0, Pins(1)),
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("ps7_srstb", 0, Pins(1)),
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("ps7_mio", 0, Pins(54)),
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("ps7_ddram", 0,
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Subsignal("addr", Pins(15)),
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Subsignal("ba", Pins(3)),
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Subsignal("cas_n", Pins(1)),
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Subsignal("ck_n", Pins(1)),
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Subsignal("ck_p", Pins(1)),
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Subsignal("cke", Pins(1)),
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Subsignal("cs_n", Pins(1)),
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Subsignal("dm", Pins(4)),
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Subsignal("dq", Pins(32)),
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Subsignal("dqs_n", Pins(4)),
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Subsignal("dqs_p", Pins(4)),
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Subsignal("odt", Pins(1)),
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Subsignal("ras_n", Pins(1)),
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Subsignal("reset_n", Pins(1)),
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Subsignal("we_n", Pins(1)),
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Subsignal("vrn", Pins(1)),
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Subsignal("vrp", Pins(1)),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("ja1", "- - - G14 E18 D20 E19 D19 - - F16 B20 F17 C20 - - E17 A20 D18 B19 - - F19 G20 F20 G19 - - J20 G18 H20 G17 - - J18 H17 H18 H16 - -"),
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("ja2", "- - - J15 L14 J16 L15 K16 - - M14 G15 M15 H15 - - N15 J14 N16 K14 - - L19 J19 L20 K19 - - M17 M20 M18 M19 - - L16 K18 L17 K17 - -"),
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("jb1", "- - - T19 T11 U12 T10 T12 - - P14 W13 R14 V12 - - U13 T14 V13 T14 - - T16 Y17 U17 Y16 - - W14 W15 Y14 V15 - - U14 U19 U15 U18 - -"),
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("jb2", "- - - R19 N17 P16 P18 P15 - - T17 R17 R18 R16 - - V17 W19 V18 W18 - - T20 W16 U20 V16 - - V20 Y19 W20 Y18 - - N20 P19 P20 N18 - -"),
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("jc1", "- - - V5 U7 U10 V7 T9 - - T5 Y13 U5 Y12 - - V11 W6 V10 V6 - - V8 Y11 W8 W11 - - U9 W9 U8 W10 - - Y9 Y6 Y8 Y7 - -"),
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# ("xadc", "N15 L14 K16 K14 N16 L15 J16 J14"),
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# ("mrcc", "H17 H16 K18 K17 U19 U18 P19 N18 Y6 Y7"),
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# ("srcc", "J18 H18 L16 L17 U14 U15 N20 P20 Y9 Y8"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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# The clock speed depends on the PS7 PLL configuration for the FCLK_CLK0 signal.
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default_clk_name = "clk100"
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default_clk_freq = 100e6
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def __init__(self, variant="z7-10", toolchain="vivado"):
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device = {
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"z7-10": "xc7z010-clg400-1",
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"z7-20": "xc7z020-clg400-3"
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}[variant]
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XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
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self.default_clk_period = 1e9 / self.default_clk_freq
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self.toolchain.bitstream_commands = [
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"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
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]
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def create_programmer(self):
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return VivadoProgrammer(flash_part="n25q128a")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True), self.default_clk_period)
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