144 lines
5.9 KiB
Python
144 lines
5.9 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk100", 0, Pins("C12"), IOStandard("LVCMOS33")),
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("user_led", 0, Pins("D21"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("B20"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("B21"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("C22"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("E22"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("C21"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("A20"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("E21"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("D23"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("E26")),
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Subsignal("rx", Pins("F25")),
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IOStandard("LVCMOS33")
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),
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("serial", 1,
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Subsignal("tx", Pins("D26")),
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Subsignal("rx", Pins("E25")),
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IOStandard("LVCMOS33")
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),
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# DDR4
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("ddr4", 0,
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Subsignal("a", Pins(
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"AF10 AC11 AD11 AD10 AC9 AD9 AB9 AF7 AE8",
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"AE7 Y12 AC7 AB7 AD13"),
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IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("AB11 AB10"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("AA9 AF9"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("AA12"), IOStandard("SSTL12_DCI")), # A16
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Subsignal("cas_n", Pins("AF13"), IOStandard("SSTL12_DCI")), # A15
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Subsignal("we_n", Pins("AA13"), IOStandard("SSTL12_DCI")), # A14
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Subsignal("cs_n", Pins("W13 AA14 AC14 AF15"), IOStandard("SSTL12_DCI")),
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Subsignal("act_n", Pins("Y8"), IOStandard("SSTL12_DCI")),
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Subsignal("alert_n", Pins("AE10"), IOStandard("SSTL12_DCI")),
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Subsignal("par", Pins("AE13"), IOStandard("SSTL12_DCI")),
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Subsignal("dm", Pins("AF3 AE5 AD6 AC6 AF2 AE3 AE6 AD5"),
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IOStandard("SSTL12_DCI")),
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Subsignal("dq", Pins(
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"W11 Y11 V7 Y7 V11 V9 V8 W8",
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"U2 V6 Y2 Y3 U5 U4 W3 Y1",
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"AA2 AB2 AE1 AE2 V2 W1 AD1 AC2",
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"W4 AA3 AD3 AC4 V3 V4 AB4 AC3",
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"AC16 AC17 AB16 AA19 AB15 AD16 AC18 AC19",
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"AF17 AE17 AF20 AD19 AE15 AE16 AF19 AD18",
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"Y18 Y17 W14 V14 AA20 AA15 V18 W16",
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"AA18 AB19 V16 W15 AB17 AA17 V19 V17"),
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IOStandard("SSTL12")),
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Subsignal("dqs_p", Pins(
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"W10 W6 AB1 AA5 AD20 AE18 W18 Y15 AF5",
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"B17 D19 L19 J15 T24 P19 R16 M25 AC8"),
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IOStandard("DIFF_HSUL_12")),
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Subsignal("dqs_n", Pins(
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"W9 W5 AC1 AB5 AE20 AF18 W19 Y16 AF4",
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"A17 D20 L20 J16 T25 P20 R17 L25 AD8"),
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IOStandard("DIFF_HSUL_12")),
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Subsignal("clk_p", Pins("AE12 AB12"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("clk_n", Pins("AF12 AC12"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("cke", Pins("AA8 AA7"), IOStandard("SSTL12_DCI")), # also AM15 for larger SODIMMs
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Subsignal("odt", Pins("Y13 AB14"), IOStandard("SSTL12_DCI")), # also AM16 for larger SODIMMs
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Subsignal("reset_n", Pins("AB6"), IOStandard("SSTL12")),
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Misc("SLEW=FAST"),
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),
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# RGMII Ethernet
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("eth_ref_clk", 0, Pins("AA23"), IOStandard("LVCMOS33")),
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("eth_clocks", 0,
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Subsignal("rx", Pins("Y23")),
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Subsignal("tx", Pins("AA24")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("AA22")),
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Subsignal("mdio", Pins("AB26")),
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Subsignal("mdc", Pins("AA25")),
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Subsignal("rx_ctl", Pins("Y25")),
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Subsignal("rx_data", Pins("W26 W25 V26 U25")),
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Subsignal("tx_ctl", Pins("U26")),
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Subsignal("tx_data", Pins("W24 Y26 Y22 Y21")),
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IOStandard("LVCMOS33")
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),
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# HyperRAM
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("hyperram", 0,
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Subsignal("clk_n", Pins("AE26")),
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Subsignal("clk_p", Pins("AD26")),
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Subsignal("rst_n", Pins("AC24")),
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Subsignal("cs_n", Pins("AC26")),
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Subsignal("dq", Pins("AE23 AD25 AF24 AE22 AF23 AF25 AE25 AD24")),
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Subsignal("rwds", Pins("AD23")),
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IOStandard("LVCMOS33")
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),
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# SD Card
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("sdcard", 0,
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Subsignal("data", Pins("E10 F8 C9 D9"), Misc("PULLUP True")),
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Subsignal("cmd", Pins("D8"), Misc("PULLUP True")),
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Subsignal("clk", Pins("D10")),
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Subsignal("cd", Pins("F9")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, device="xc7k160tffg676-1"):
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XilinxPlatform.__init__(self, device, _io, toolchain="vivado")
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.6 [get_iobanks 32]")
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self.add_platform_command("set_property INTERNAL_VREF 0.6 [get_iobanks 33]")
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self.add_platform_command("set_property INTERNAL_VREF 0.6 [get_iobanks 34]")
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft4232.cfg", "bscan_spi_xc7k100t.bit")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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