106 lines
4.2 KiB
Python
Executable File
106 lines
4.2 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import efinix_titanium_ti60_f225_dev_kit
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from litex.build.generic_platform import *
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.soc import SoCRegion
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from litehyperbus.core.hyperbus import HyperRAM
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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clk25 = platform.request("clk25")
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rst_n = platform.request("user_btn", 0)
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# PLL
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self.submodules.pll = pll = TITANIUMPLL(platform)
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self.comb += pll.reset.eq(~rst_n)
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pll.register_clkin(clk25, 25e6)
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# You can use CLKOUT0 only for clocks with a maximum frequency of 4x
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# (integer) of the reference clock. If all your system clocks do not fall within
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# this range, you should dedicate one unused clock for CLKOUT0.
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pll.create_clkout(None, 25e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), with_spi_flash=False, with_hyperram=False, **kwargs):
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platform = efinix_titanium_ti60_f225_dev_kit.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Efinix Titanium Ti60 F225 Dev Kit",
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ident_version = True,
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**kwargs
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)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import W25Q64JW
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=W25Q64JW(Codes.READ_1_1_1), with_master=True)
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if with_hyperram:
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self.submodules.hyperram = HyperRAM(platform.request("hyperram"), latency=7)
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self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=16*1024*1024))
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Efinix Titanium Ti60 F225 Dev Kit")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--flash", action="store_true", help="Flash bitstream")
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parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
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parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
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parser.add_argument("--with-hyperram", action="store_true", help="Enable HyperRAM")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_spi_flash = args.with_spi_flash,
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with_hyperram = args.with_hyperram,
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**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, f"{soc.build_name}.bit"))
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if args.flash:
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from litex.build.openfpgaloader import OpenFPGALoader
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prog = OpenFPGALoader("titanium_ti60_f225")
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prog.flash(0, os.path.join(builder.gateware_dir, f"{soc.build_name}.hex"))
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if __name__ == "__main__":
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main()
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