135 lines
5.6 KiB
Python
Executable File
135 lines
5.6 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Primesh Pinto <primeshp@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex_boards.platforms import seeedstudio_spartan_edge_accelerator
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser,WS2812
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from litex.soc.cores.video import *
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# Serial Port --------------------------------------------------------------------------------------
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_serial_io = [
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# Use J10 connectors 0/1 IOs + GND.
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("serial", 0,
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Subsignal("tx", Pins("j10:j10_0")),
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Subsignal("rx", Pins("j10:j10_1")),
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IOStandard("LVCMOS33")
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),
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]
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_video_pll):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_hdmi5x = ClockDomain()
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# # #
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clk100 = platform.request("clk100")
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rst_n = platform.request("rst_n")
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk100, sys_clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if with_video_pll:
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self.submodules.video_pll = video_pll = S7PLL(speedgrade=-1)
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video_pll.reset.eq(~rst_n | self.rst)
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video_pll.register_clkin(clk100, 100e6)
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video_pll.create_clkout(self.cd_hdmi, 25e6)
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video_pll.create_clkout(self.cd_hdmi5x, 5*25e6)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(100e6),
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with_led_chaser = True,
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with_jtagbone = False,
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with_video_terminal = True,
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with_neopixel = False,
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**kwargs):
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platform = seeedstudio_spartan_edge_accelerator.Platform()
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platform.add_extension(_serial_io)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Seeedstudio Spartan Edge Accelerator", **kwargs)
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# Jtagbone ---------------------------------------------------------------------------------
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if with_jtagbone:
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self.add_jtagbone()
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq
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)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal:
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self.submodules.videophy = VideoHDMIPHY(platform.request("hdmi"), clock_domain="hdmi")
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self.add_video_colorbars(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
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#self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi") #Fixme Not enough BRAM
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# Neopixel ---------------------------------------------------------------------------------
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# To test Nexpixel with LiteX BIOS:
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# - mem_list (to get ws2812_base).
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# - mem_write <ws2812_base> 0x00100000
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if with_neopixel:
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self.submodules.ws2812 = WS2812(platform.request("rgb"), nleds=2, sys_clk_freq=sys_clk_freq)
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self.bus.add_slave(name="ws2812", slave=self.ws2812.bus, region=SoCRegion(size=2*4))
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Spartan Edge Accelerator")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
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target_group.add_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
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target_group.add_argument("--with-video-terminal", action="store_true", help="Enable Video Colorbars (HDMI).")
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target_group.add_argument("--with-neopixel", action="store_true", help="Enable onboard 2 Neopixels Leds.")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_jtagbone = args.with_jtagbone,
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with_video_terminal = args.with_video_terminal,
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with_neopixel = args.with_neopixel,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder_kwargs = vivado_build_argdict(args)
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if args.build:
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builder.build(**builder_kwargs)
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if __name__ == "__main__":
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main()
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