105 lines
3.7 KiB
Python
Executable File
105 lines
3.7 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2019 msloniewski <marcin.sloniewski@gmail.com>
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# License: BSD
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import argparse
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from migen import *
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from litex_boards.platforms import de10lite
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import IS42S16320
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from litedram.phy import GENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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# # #
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self.cd_sys.clk.attr.add("keep")
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self.cd_sys_ps.clk.attr.add("keep")
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self.cd_por.clk.attr.add("keep")
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# power on rst
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rst_n = Signal()
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self.sync.por += rst_n.eq(1)
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self.comb += [
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self.cd_por.clk.eq(self.cd_sys.clk),
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self.cd_sys.rst.eq(~rst_n),
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self.cd_sys_ps.rst.eq(~rst_n)
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]
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# sys clk / sdram clk
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clk50 = platform.request("clk50")
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self.comb += self.cd_sys.clk.eq(clk50)
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self.specials += \
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Instance("ALTPLL",
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p_BANDWIDTH_TYPE = "AUTO",
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p_CLK0_DIVIDE_BY = 1,
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p_CLK0_DUTY_CYCLE = 50,
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p_CLK0_MULTIPLY_BY = 1,
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p_CLK0_PHASE_SHIFT = "-10000",
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p_COMPENSATE_CLOCK = "CLK0",
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p_INCLK0_INPUT_FREQUENCY = 20000,
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p_INTENDED_DEVICE_FAMILY = "MAX 10",
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p_LPM_TYPE = "altpll",
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p_OPERATION_MODE = "NORMAL",
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i_INCLK = clk50,
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o_CLK = self.cd_sys_ps.clk,
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i_ARESET = ~rst_n,
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i_CLKENA = 0x3f,
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i_EXTCLKENA = 0xf,
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i_FBIN = 1,
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i_PFDENA = 1,
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i_PLLENA = 1,
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)
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self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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def __init__(self, sys_clk_freq=int(50e6), **kwargs):
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assert sys_clk_freq == int(50e6)
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platform = de10lite.Platform()
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=0x8000,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
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sdram_module = IS42S16320(self.clk_freq, "1:1")
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self.register_sdram(self.sdrphy,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Lite")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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