131 lines
4.5 KiB
Python
131 lines
4.5 KiB
Python
from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import IceStormProgrammer
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_io = [
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# Clk
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("clk12", 0, Pins("35"), IOStandard("LVCMOS33")),
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# LEDs
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("user_led_n", 0, Pins("39"), IOStandard("LVCMOS33")),
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("rgb_led", 0,
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Subsignal("r", Pins("41")),
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Subsignal("g", Pins("40")),
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Subsignal("b", Pins("39")),
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IOStandard("LVCMOS33")
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),
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# Buttons
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("user_sw", 0, Pins("23"), IOStandard("LVCMOS33")),
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("user_sw", 1, Pins("25"), IOStandard("LVCMOS33")),
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("user_sw", 2, Pins("34"), IOStandard("LVCMOS33")),
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("user_sw", 3, Pins("43"), IOStandard("LVCMOS33"))
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]
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spiflash = [
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# Only usable in PROG FLASH mode and J7 attached (see PCB silkscreen).
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("spiflash", 0,
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Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("14"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("17"), IOStandard("LVCMOS33")),
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),
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]
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serial = [
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("serial", 0,
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Subsignal("tx", Pins("J3:0")),
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Subsignal("rx", Pins("J3:1")),
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IOStandard("LVCMOS33")
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),
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("serial", 1,
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Subsignal("tx", Pins("J3:2")),
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Subsignal("rx", Pins("J3:3")),
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IOStandard("LVCMOS33")
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)
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]
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_connectors = [
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# Many pins on the AARDVARK, PMOD, J52/HEADER A, and J2/HEADER B connectors
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# are multiplexed with other I/O or connector pins. For completeness, all
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# pins are exposed here except Vdd, NC, and GND. Pin order is as specified
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# on the schematic (except for PMOD, which uses Digilent's numbering).
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# AARDVARK connector omitted- although sysCONFIG pins are exposed on this
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# header (which can be used as GPIO), it is meant for flashing using an
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# external programmer rather than as an I/O port.
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# PMOD connector shares pins with sysCONFIG- make sure to remove jumper
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# J7 if using the PMOD. TODO: Perhaps it would be better to split into two
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# single 6-pin PMODs.
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#
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# PMOD pinout (using ICE40 pin names):
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# 1, 2, 3, 4- SPI_SS, SPI_SI, SPI_SO, SPI_SCK
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# 5, 6, 7, 8- Free
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("PMOD", "16 17 14 15 27 26 32 31"),
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#Silk: SS MOSI MISO SCK 38B 39A 43A 42B
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# J52 exposes LEDs and sysCONFIG pins (yet again). Make sure to remove
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# jumper J7 if using the PMOD. Pin order is as follows (right to left):
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# 12 10 8 6 4 2
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# 11 9 7 5 3 1
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#
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# J52's pinout (using ICE40 pin names for SPI flash):
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# 1, 2- Vdd
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# 3, 4- rgb_led.b, SPI_SI
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# 5, 6- rgb_led.g, SPI_SO
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# 7, 8- GND, SPI_SCK
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# 9, 10- rgb_led.r, SPI_SS
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# 11, 12- GND
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# 3 4 5 6 8 9 10
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("J52", "39 17 40 14 15 41 16"),
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# Pin order of J2, and J3 are as follows (left to right/top to bottom):
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# 2 4 6 8 10 12 14 16 18 20
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# 1 3 5 7 9 11 13 15 17 19
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#
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# J2's pinout is shared by many things. Entire pinout listed follows:
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# 1, 2- Vdd
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# 3, 4- user_sw0, NC
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# 5, 6- user_sw1, NC
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# 7, 8- PMOD D5, Free
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# 9, 10- PMOD D4, Free
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# 11, 12- PMOD D6, Free
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# 13, 14- PMOD D7, Free
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# 15, 16- Free, 12.00 clock
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# 17, 18- user_sw2, GND
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# 19, 20- user_sw3, GND
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# 3 5 7 8 9 10 11 12 13 14 15 16 17 19
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("J2", "23 25 26 36 27 42 32 38 31 28 37 35 34 43"),
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# Silk:37A 36B 39A 48B 38B 51A 43A 50B 42B 41A 45A_G1 ICE_CLK 44B 49A
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# index: 0 1 2 3 4 5 6 7 8 9 10 11 12 13
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# Bank2: 4 3 48 45 47 44 46 2
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# Bank1: 12 21 13 20 19 18 11 10 9 6
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# J3's pinout is all Free, except 1 (Vdd) and 19 (GND).
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# 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20
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("J3", "12 4 21 3 13 48 20 45 19 47 18 44 11 46 10 2 9 6"),
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# Silk:22A 8A 23B 9B 24A 4A 25B_G3 5B 29B 2A 31B 3B_G6 20A 0A 18A 6A 16A 13B
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# index: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
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]
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class Platform(LatticePlatform):
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default_clk_name = "clk12"
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default_clk_period = 1e9/12e6
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def __init__(self, toolchain="icestorm"):
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LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain=toolchain)
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self.add_extension(serial)
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self.add_extension(spiflash)
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def create_programmer(self):
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return IceStormProgrammer()
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6)
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