144 lines
5.4 KiB
Python
144 lines
5.4 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 Tom Keddie <git@bronwenandtom.com>
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# The Pano Logic Zero Client G2 is a thin commercial client from Pano Logic that can be repurposed
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# as a generic development board thanks to reverse engineering efforts than can be found at:
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# https://github.com/tomverbeure/panologic-g2
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk125", 0, Pins("Y13"), IOStandard("LVCMOS33")),
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("rst_n", 0, Pins("AB14"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("E12"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("H13"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("F13"), IOStandard("LVCMOS33")),
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# Buttons
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("user_btn_n", 0, Pins("H12"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0, # hdmi
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Subsignal("tx", Pins("AB19")),
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Subsignal("rx", Pins("AA21")),
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IOStandard("LVCMOS33")
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),
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# Serial
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("serial", 1, # dvi
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Subsignal("tx", Pins("C14")),
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Subsignal("rx", Pins("C17")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("T5"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("Y21"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("AB20"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("AA20"), IOStandard("LVCMOS33"))
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),
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# DDR2 SDRAM
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("ddram_clock_a", 0,
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Subsignal("p", Pins("H20")),
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Subsignal("n", Pins("J19")),
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IOStandard("DIFF_SSTL18_II"), Misc("IN_TERM=NONE")
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),
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("ddram_a", 0,
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Subsignal("a", Pins(
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"F21 F22 E22 G20 F20 K20 K19 E20",
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"C20 C22 G19 F19 D22"),
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IOStandard("SSTL18_II")),
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Subsignal("ba", Pins("J17 K17 H18"), IOStandard("SSTL18_II")),
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Subsignal("ras_n", Pins("H21"), IOStandard("SSTL18_II")),
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Subsignal("cas_n", Pins("H22"), IOStandard("SSTL18_II")),
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Subsignal("we_n", Pins("H19"), IOStandard("SSTL18_II")),
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Subsignal("dm", Pins("M20 L19"), IOStandard("SSTL18_II")),
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Subsignal("dq", Pins(
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"N20 N22 M21 M22 J20 J22 K21 K22",
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"P21 P22 R20 R22 U20 U22 V21 V22"),
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IOStandard("SSTL18_II")),
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Subsignal("dqs", Pins("T21 L20"), IOStandard("DIFF_SSTL18_II")),
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Subsignal("dqs_n", Pins("T22 L22"), IOStandard("DIFF_SSTL18_II")),
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Subsignal("cke", Pins("D21"), IOStandard("SSTL18_II")),
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Subsignal("odt", Pins("G22"), IOStandard("SSTL18_II")),
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),
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("ddram_clock_b", 0,
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Subsignal("p", Pins("H4")),
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Subsignal("n", Pins("H3")),
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IOStandard("DIFF_SSTL18_II"), Misc("IN_TERM=NONE")
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),
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("ddram_b", 0,
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Subsignal("a", Pins(
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"H2 H1 H5 K6 F3 K3 J4 H6",
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"E3 E1 G4 C1 D1"),
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IOStandard("SSTL18_II")),
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Subsignal("ba", Pins("G3 G1 F1"), IOStandard("SSTL18_II")),
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Subsignal("ras_n", Pins("K5"), IOStandard("SSTL18_II")),
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Subsignal("cas_n", Pins("K4"), IOStandard("SSTL18_II")),
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Subsignal("we_n", Pins("F2"), IOStandard("SSTL18_II")),
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Subsignal("dm", Pins("M3 L4"), IOStandard("SSTL18_II")),
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Subsignal("dq", Pins(
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"N3 N1 M2 M1 J3 J1 K2 K1",
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"P2 P1 R3 R1 U3 U1 V2 V1"),
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IOStandard("SSTL18_II")),
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Subsignal("dqs", Pins("T2 L3"), IOStandard("DIFF_SSTL18_II")),
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Subsignal("dqs_n", Pins("T1 L1"), IOStandard("DIFF_SSTL18_II")),
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Subsignal("cke", Pins("D2"), IOStandard("SSTL18_II")),
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Subsignal("odt", Pins("J6"), IOStandard("SSTL18_II")),
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),
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# GMII Ethernet
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("eth_rst_n", 0, Pins("R11"), IOStandard("LVCMOS33")),
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("eth_clocks", 0,
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Subsignal("tx", Pins("Y11")),
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Subsignal("gtx", Pins("AA12")),
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Subsignal("rx", Pins("AB11")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("R11")),
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Subsignal("int_n", Pins("AA4")),
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Subsignal("mdio", Pins("AA2")),
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Subsignal("mdc", Pins("AB6")),
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Subsignal("rx_dv", Pins("Y7")),
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Subsignal("rx_er", Pins("Y8")),
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Subsignal("rx_data", Pins("Y3 Y4 R9 R7 V9 R8 U9 Y9")),
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Subsignal("tx_en", Pins("AA8")),
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Subsignal("tx_er", Pins("AB8")),
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Subsignal("tx_data", Pins("AB2 AB3 AB4 AB7 AB9 AB10 T7 Y10")),
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Subsignal("col", Pins("V7")),
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Subsignal("crs", Pins("W4")),
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IOStandard("LVCMOS33")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk125"
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default_clk_period = 1e9/125e6
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def __init__(self, revision="c", toolchain="ise"):
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assert revision in ["b", "c"]
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device = {"b": "xc6slx150-2-fgg484", "c": "xc6slx100-2-fgg484"}[revision]
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XilinxPlatform.__init__(self, device, _io, toolchain=toolchain)
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self.add_platform_command("""CONFIG VCCAUX="2.5";""")
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self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
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def create_programmer(self):
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return OpenOCD("openocd_xc6_ft232.cfg")
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