127 lines
5.5 KiB
Python
Executable File
127 lines
5.5 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Rakesh Peter <rakesh@stanproc.in>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex_boards.platforms import digilent_pynq_z1
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.interconnect import axi
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from litex.soc.interconnect import wishbone
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import *
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from litex.soc.cores.video import VideoS7HDMIPHY
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from litex.soc.cores.led import LedChaser
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, toolchain, use_ps7_clk=False, with_video_pll=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_hdmi5x = ClockDomain()
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# # #
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# Clk
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clk125 = platform.request("sysclk")
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# PLL
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if use_ps7_clk:
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assert sys_clk_freq == 125e6
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self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
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self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
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else:
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk125, 125e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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# Video PLL.
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if with_video_pll:
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self.submodules.video_pll = video_pll = S7MMCM(speedgrade=-1)
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video_pll.reset.eq(self.rst)
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video_pll.register_clkin(clk125, 125e6)
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video_pll.create_clkout(self.cd_hdmi, 40e6)
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video_pll.create_clkout(self.cd_hdmi5x, 5*40e6)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_led_chaser=True,
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with_video_terminal=False, with_video_framebuffer=False, **kwargs):
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platform = digilent_pynq_z1.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, toolchain, with_video_pll=with_video_terminal)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on PYNQ Z1", **kwargs)
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# Zynq7000 Integration ---------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "zynq7000":
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# Get and set the pre-generated .xci FIXME: change location? add it to the repository?
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os.system("wget https://github.com/litex-hub/litex-boards/files/8339591/zybo_z7_ps7.txt)")
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os.makedirs("xci", exist_ok=True)
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os.system("mv zybo_z7_ps7.txt xci/zybo_z7_ps7.xci")
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self.cpu.set_ps7_xci("xci/zybo_z7_ps7.xci")
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# Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one)
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wb_gp0 = wishbone.Interface()
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self.submodules += axi.AXI2Wishbone(
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axi = self.cpu.add_axi_gp_master(),
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wishbone = wb_gp0,
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base_address = 0x43c00000)
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self.bus.add_master(master=wb_gp0)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal:
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self.submodules.videophy = VideoS7HDMIPHY(platform.request("hdmi_tx"), clock_domain="hdmi")
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on PYNQ Z1")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
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target_group.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_video_terminal = args.with_video_terminal,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**vivado_build_argdict(args), run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"), device=1)
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if __name__ == "__main__":
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main()
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