232 lines
9.4 KiB
Python
Executable File
232 lines
9.4 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2015 Robert Jordens <jordens@gmail.com>
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# Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
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# Copyright (c) 2015 Yann Sionneau <yann.sionneau@gmail.com>
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# Copyright (c) 2016-2017 Tim 'mithro' Ansell <mithro@mithis.com>
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# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from fractions import Fraction
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import atlys
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT47H64M16
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from litedram.phy import s6ddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sdram_half = ClockDomain()
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self.clock_domains.cd_sdram_full_wr = ClockDomain()
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self.clock_domains.cd_sdram_full_rd = ClockDomain()
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self.reset = Signal()
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# # #
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# Input clock ------------------------------------------------------------------------------
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clk100_freq = int(100e6)
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clk100 = platform.request("clk100")
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clk100b = Signal()
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self.specials += Instance("BUFIO2",
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p_DIVIDE=1, p_DIVIDE_BYPASS="TRUE",
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p_I_INVERT="FALSE",
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i_I=clk100, o_DIVCLK=clk100b)
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# PLL --------------------------------------------------------------------------------------
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pll_lckd = Signal()
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pll_fb = Signal()
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pll_sdram_full = Signal()
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pll_sdram_half_a = Signal()
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pll_sdram_half_b = Signal()
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pll_unused = Signal()
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pll_sys = Signal()
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pll_periph = Signal()
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f0 = clk100_freq
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f = Fraction(int(sys_clk_freq), int(f0))
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n, m = f.denominator, f.numerator
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assert f0 / n * m == sys_clk_freq
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p = 8
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self.specials.pll = Instance(
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"PLL_ADV",
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name="crg_pll_adv",
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p_SIM_DEVICE="SPARTAN6", p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
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p_REF_JITTER=.01,
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i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
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p_DIVCLK_DIVIDE=1,
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# Input Clocks (100MHz)
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i_CLKIN1=clk100b,
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p_CLKIN1_PERIOD=1e9/f0,
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i_CLKIN2=0,
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p_CLKIN2_PERIOD=0.,
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i_CLKINSEL=1,
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# Feedback
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i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
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p_CLK_FEEDBACK="CLKFBOUT",
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p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
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# (300MHz) sdram wr rd
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o_CLKOUT0=pll_sdram_full, p_CLKOUT0_DUTY_CYCLE=.5,
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p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//4,
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# unused?
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o_CLKOUT1=pll_unused, p_CLKOUT1_DUTY_CYCLE=.5,
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p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=15,
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# (150MHz) sdram_half - sdram dqs adr ctrl
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o_CLKOUT2=pll_sdram_half_a, p_CLKOUT2_DUTY_CYCLE=.5,
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p_CLKOUT2_PHASE=270., p_CLKOUT2_DIVIDE=p//2,
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# (150Mhz) off-chip ddr
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o_CLKOUT3=pll_sdram_half_b, p_CLKOUT3_DUTY_CYCLE=.5,
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p_CLKOUT3_PHASE=250., p_CLKOUT3_DIVIDE=p//2,
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# ( 50MHz) periph
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o_CLKOUT4=pll_periph, p_CLKOUT4_DUTY_CYCLE=.5,
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p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=20,
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# ( 75MHz) sysclk
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o_CLKOUT5=pll_sys, p_CLKOUT5_DUTY_CYCLE=.5,
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p_CLKOUT5_PHASE=0., p_CLKOUT5_DIVIDE=p//1,
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)
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# Power on reset
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reset = ~platform.request("cpu_reset") | self.reset
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self.clock_domains.cd_por = ClockDomain()
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por = Signal(max=1 << 11, reset=(1 << 11) - 1)
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self.sync.por += If(por != 0, por.eq(por - 1))
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self.specials += AsyncResetSynchronizer(self.cd_por, reset)
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# System clock
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self.specials += Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk)
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self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | (por > 0))
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# SDRAM clocks -----------------------------------------------------------------------------
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self.clk4x_wr_strb = Signal()
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self.clk4x_rd_strb = Signal()
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# SDRAM full clock
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self.specials += Instance("BUFPLL", name="sdram_full_bufpll",
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p_DIVIDE = 4,
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i_PLLIN = pll_sdram_full, i_GCLK=self.cd_sys.clk,
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i_LOCKED = pll_lckd,
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o_IOCLK = self.cd_sdram_full_wr.clk,
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o_SERDESSTROBE = self.clk4x_wr_strb)
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self.comb += [
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self.cd_sdram_full_rd.clk.eq(self.cd_sdram_full_wr.clk),
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self.clk4x_rd_strb.eq(self.clk4x_wr_strb),
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]
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# SDRAM_half clock
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self.specials += Instance("BUFG", name="sdram_half_a_bufpll",
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i_I=pll_sdram_half_a, o_O=self.cd_sdram_half.clk)
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clk_sdram_half_shifted = Signal()
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self.specials += Instance("BUFG", name="sdram_half_b_bufpll",
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i_I=pll_sdram_half_b, o_O=clk_sdram_half_shifted)
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output_clk = Signal()
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clk = platform.request("ddram_clock")
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self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
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p_INIT=0, p_SRTYPE="SYNC",
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i_D0=1, i_D1=0, i_S=0, i_R=0, i_CE=1,
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i_C0=clk_sdram_half_shifted,
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i_C1=~clk_sdram_half_shifted,
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o_Q=output_clk)
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self.specials += Instance("OBUFDS", i_I=output_clk, o_O=clk.p, o_OB=clk.n)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, with_ethernet=True, with_etherbone=False, eth_phy=0, **kwargs):
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sys_clk_freq = int(75e6)
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platform = atlys.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Atlys",
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
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# DDR2 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(platform.request("ddram"),
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memtype = "DDR2",
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rd_bitslip = 0,
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wr_bitslip = 4,
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dqs_ddr_alignment = "C0")
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self.comb += [
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self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
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self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
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]
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT47H64M16(sys_clk_freq, "1:2"),
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l2_cache_size = kwargs.get("l2_size", 8192),
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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from liteeth.phy import LiteEthPHYGMIIMII
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self.submodules.ethphy = LiteEthPHYGMIIMII(
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clock_pads = self.platform.request("eth_clocks", eth_phy),
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pads = self.platform.request("eth", eth_phy),
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clk_freq = int(self.sys_clk_freq))
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy)
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self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
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self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
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self.platform.add_platform_command("""
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NET "{eth_clocks_rx}" CLOCK_DEDICATED_ROUTE = FALSE;
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NET "{eth_clocks_tx}" CLOCK_DEDICATED_ROUTE = FALSE;
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""",
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eth_clocks_rx=platform.lookup_request("eth_clocks").rx,
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eth_clocks_tx=platform.lookup_request("eth_clocks").tx,
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)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Atlys")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args), )
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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