211 lines
9.9 KiB
Python
Executable File
211 lines
9.9 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import nexys_video
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoS7HDMIPHY
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT41K256M16
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from litedram.phy import s7ddrphy
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from liteeth.phy.s7rgmii import LiteEthPHYRGMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, toolchain="vivado", with_sata_pll_refclk=False, with_video_pll=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_hdmi5x = ClockDomain()
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self.clock_domains.cd_clk100 = ClockDomain()
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# # #
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# Clk / Rst.
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clk100 = platform.request("clk100")
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rst_n = platform.request("cpu_reset")
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# PLL.
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if toolchain == "vivado":
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self.submodules.pll = pll = S7MMCM(speedgrade=-1)
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else:
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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pll.create_clkout(self.cd_clk100, 100e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# SATA PLL.
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if with_sata_pll_refclk:
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self.clock_domains.cd_sata_refclk = ClockDomain()
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pll.create_clkout(self.cd_sata_refclk, 150e6)
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platform.add_platform_command("set_property SEVERITY {{WARNING}} [get_drc_checks REQP-49]")
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# Video PLL.
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if with_video_pll:
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self.submodules.video_pll = video_pll = S7MMCM(speedgrade=-1)
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video_pll.reset.eq(~rst_n | self.rst)
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video_pll.register_clkin(clk100, 100e6)
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video_pll.create_clkout(self.cd_hdmi, 40e6)
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video_pll.create_clkout(self.cd_hdmi5x, 5*40e6)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False,
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with_led_chaser=True, with_sata=False, sata_gen="gen2", with_sata_pll_refclk=False, vadj="1.2V", with_video_terminal=False,
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with_video_framebuffer=False, **kwargs):
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platform = nexys_video.Platform(toolchain=toolchain)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Nexys Video",
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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with_video_pll = (with_video_terminal or with_video_framebuffer)
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self.submodules.crg = _CRG(platform, sys_clk_freq, toolchain, with_sata_pll_refclk=with_sata_pll_refclk, with_video_pll=with_video_pll)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K256M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet ---------------------------------------------------------------------------------
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if with_ethernet:
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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self.add_ethernet(phy=self.ethphy)
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# SATA -------------------------------------------------------------------------------------
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if with_sata:
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from litex.build.generic_platform import Subsignal, Pins
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from litesata.phy import LiteSATAPHY
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# IOs
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_sata_io = [
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# AB09-FMCRAID / https://www.dgway.com/AB09-FMCRAID_E.html
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("fmc2sata", 0,
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Subsignal("clk_p", Pins("LPC:GBTCLK0_M2C_P")),
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Subsignal("clk_n", Pins("LPC:GBTCLK0_M2C_N")),
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Subsignal("tx_p", Pins("LPC:DP0_C2M_P")),
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Subsignal("tx_n", Pins("LPC:DP0_C2M_N")),
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Subsignal("rx_p", Pins("LPC:DP0_M2C_P")),
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Subsignal("rx_n", Pins("LPC:DP0_M2C_N"))
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),
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]
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platform.add_extension(_sata_io)
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# PHY
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self.submodules.sata_phy = LiteSATAPHY(platform.device,
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refclk = None if not with_sata_pll_refclk else self.crg.cd_sata_refclk.clk,
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pads = platform.request("fmc2sata"),
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gen = sata_gen,
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clk_freq = sys_clk_freq,
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data_width = 16)
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# Core
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self.add_sata(phy=self.sata_phy, mode="read+write")
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal or with_video_framebuffer:
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self.submodules.videophy = VideoS7HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# VADJ -------------------------------------------------------------------------------------
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vadj_map = {"1.2V": 0b00, "1.8V": 0b01, "2.5V": 0b10, "3.3V": 0b11}
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platform.request_all("vadj").eq(vadj_map[vadj])
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Nexys Video")
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parser.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado or symbiflow).")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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sdopts = parser.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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parser.add_argument("--with-sata", action="store_true", help="Enable SATA support (over FMCRAID).")
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parser.add_argument("--sata-gen", default="2", help="SATA Gen.", choices=["1", "2"])
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parser.add_argument("--with-sata-pll-refclk", action="store_true", help="Generate SATA RefClk from PLL.")
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parser.add_argument("--vadj", default="1.2V", help="FMC VADJ value.", choices=["1.2V", "1.8V", "2.5V", "3.3V"])
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viopts = parser.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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toolchain = args.toolchain,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_sata = args.with_sata,
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sata_gen = "gen" + args.sata_gen,
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with_sata_pll_refclk = args.with_sata_pll_refclk,
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vadj = args.vadj,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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**soc_core_argdict(args)
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)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
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builder.build(**builder_kwargs, run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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