168 lines
7.1 KiB
Python
Executable File
168 lines
7.1 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 Vamsi K Vytla <vamsi.vytla@gmail.com>
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# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import ac701
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.common import PHYPadsReducer
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from litedram.modules import MT8JTF12864
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from litedram.phy import s7ddrphy
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from liteeth.phy.a7_gtp import QPLLSettings, QPLL
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from liteeth.phy.a7_1000basex import A7_1000BASEX
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from liteeth.phy.s7rgmii import LiteEthPHYRGMII
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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# # #
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(platform.request("cpu_reset") | self.rst)
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pll.register_clkin(platform.request("clk200"), 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, eth_phy="rgmii",
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with_led_chaser=True, with_pcie=False, **kwargs):
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platform = ac701.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on AC701",
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
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pads = PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT8JTF12864(sys_clk_freq, "1:4"),
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size = 0x40000000,
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet ---------------------------------------------------------------------------------
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if with_ethernet:
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# RGMII Ethernet PHY -------------------------------------------------------------------
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if eth_phy == "rgmii":
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# phy
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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# 1000BaseX Ethernet PHY ---------------------------------------------------------------
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if eth_phy == "1000basex":
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# phy
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self.comb += self.platform.request("sfp_mgt_clk_sel0", 0).eq(0)
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self.comb += self.platform.request("sfp_mgt_clk_sel1", 0).eq(0)
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self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0)
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qpll_settings = QPLLSettings(
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refclksel = 0b001,
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fbdiv = 4,
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fbdiv_45 = 5,
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refclk_div = 1)
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refclk125 = self.platform.request("gtp_refclk")
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refclk125_se = Signal()
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self.specials += \
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Instance("IBUFDS_GTE2",
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i_CEB = 0,
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i_I = refclk125.p,
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i_IB = refclk125.n,
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o_O = refclk125_se)
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qpll = QPLL(refclk125_se, qpll_settings)
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self.submodules += qpll
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self.submodules.ethphy = A7_1000BASEX(
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qpll_channel = qpll.channels[0],
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data_pads = self.platform.request("sfp", 0),
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sys_clk_freq = self.clk_freq)
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self.add_ethernet(phy=self.ethphy)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on AC701")
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builder_args(parser)
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soc_core_args(parser)
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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parser.add_argument("--eth-phy", default="rgmii", help="Select Ethernet PHY (rgmii or 1000basex).")
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parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
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parser.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_ethernet = args.with_ethernet,
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eth_phy = args.eth_phy,
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with_pcie = args.with_pcie,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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