161 lines
5.1 KiB
Python
161 lines
5.1 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Basel Sayeh <Basel.Sayeh@hotmail.com>
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# Copyright (c) 2021 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("clk50", 0, Pins("T2"), IOStandard("3.3-V LVTTL")),
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# Button
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("key", 0, Pins("Y13"), IOStandard("3.3-V LVTTL")),
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("key", 1, Pins("W13"), IOStandard("3.3-V LVTTL")),
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# SPIFlash (W25Q64)
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("spiflash", 0,
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# clk
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Subsignal("cs_n", Pins("E2")),
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Subsignal("clk", Pins("K2")),
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Subsignal("mosi", Pins("D1")),
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Subsignal("miso", Pins("E2")),
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IOStandard("3.3-V LVTTL"),
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),
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# SDR SDRAM
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("sdram_clock", 0, Pins("Y6"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins(
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"V2 V1 U2 U1 V3 V4 Y2 AA1",
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"Y3 V5 W1 Y4 V6")),
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Subsignal("ba", Pins("Y1 W2")),
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Subsignal("cs_n", Pins("AA3")),
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Subsignal("cke", Pins("W6")),
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Subsignal("ras_n", Pins("AB3")),
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Subsignal("cas_n", Pins("AA4")),
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Subsignal("we_n", Pins("AB4")),
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Subsignal("dq", Pins(
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"AA10 AB9 AA9 AB8 AA8 AB7 AA7 AB5",
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"Y7 W8 Y8 V9 V10 Y10 W10 V11")),
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Subsignal("dm", Pins("AA5 W7")),
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IOStandard("3.3-V LVTTL")
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),
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]
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# The connectors are named after the daughterboard, not the core board
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# because on the different core boards the names vary, but on the
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# daughterboard they stay the same, which we need to connect the
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# daughterboard peripherals to the core board.
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# On this board J2 is U7 and J3 is U8
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_connectors = [
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("J2", {
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# odd row even row
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7: "R1", 8: "R2",
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9: "P1", 10: "P2",
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11: "N1", 12: "N2",
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13: "M1", 14: "M2",
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15: "J1", 16: "J2",
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17: "H1", 18: "H2",
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19: "F1", 20: "F2",
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21: "E1", 22: "D2",
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23: "C1", 24: "C2",
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25: "B1", 26: "B2",
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27: "B3", 28: "A3",
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29: "B4", 30: "A4",
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31: "C4", 32: "C3",
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33: "B5", 34: "A5",
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35: "B6", 36: "A6",
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37: "B7", 38: "A7",
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39: "B8", 40: "A8",
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41: "B9", 42: "A9",
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43: "B10", 44: "A10",
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45: "B13", 46: "A13",
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47: "B14", 48: "A14",
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49: "B15", 50: "A15",
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51: "B16", 52: "A16",
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53: "B17", 54: "A17",
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55: "B18", 56: "A18",
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57: "B19", 58: "A19",
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59: "B20", 60: "A20",
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}),
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("J3", {
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# odd row even row
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7: "AA13", 8: "AB13",
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9: "AA14", 10: "AB14",
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11: "AA15", 12: "AB15",
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13: "AA16", 14: "AB16",
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15: "AA17", 16: "AB17",
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17: "AA18", 18: "AB18",
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19: "AA19", 20: "AB19",
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21: "AA20", 22: "AB20",
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23: "Y22", 24: "Y21",
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25: "W22", 26: "W21",
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27: "V22", 28: "V21",
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29: "U22", 30: "U21",
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31: "R22", 32: "R21",
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33: "P22", 34: "P21",
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35: "N22", 36: "N21",
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37: "M22", 38: "M21",
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39: "L22", 40: "L21",
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41: "K22", 42: "K21",
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43: "J22", 44: "J21",
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45: "H22", 46: "H21",
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47: "F22", 48: "F21",
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49: "E22", 50: "E21",
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51: "D22", 52: "D21",
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53: "C22", 54: "C21",
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55: "B22", 56: "B21",
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57: "N20", 58: "N19",
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59: "M20", 60: "M19",
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})
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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core_resources = [
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("user_led", 0, Pins("E4"), IOStandard("3.3-V LVTTL")),
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("serial", 0,
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Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")),
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Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL"))
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),
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]
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def __init__(self, variant="ep4ce15", with_daughterboard=False):
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device = {
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"ep4ce15": "EP4CE15F23C8",
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"ep4ce55": "EP4CE55F23C8"
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}[variant]
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io = _io
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connectors = _connectors
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if with_daughterboard:
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from litex_boards.platforms.qmtech_daughterboard import QMTechDaughterboard
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daughterboard = QMTechDaughterboard(IOStandard("3.3-V LVTTL"))
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io += daughterboard.io
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connectors += daughterboard.connectors
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else:
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io += self.core_resources
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AlteraPlatform.__init__(self, device, io, connectors)
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if with_daughterboard:
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# an ethernet pin takes K22, so make it available
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self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
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def create_programmer(self):
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return USBBlaster()
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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