Florent Kermarrec 12b91eccdc digilent_arty: Remove yosys+nextpnr INTERNAL_VREF constraint skip (now directly done in LiteX).		2022-02-14 10:45:29 +01:00
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platforms	digilent_arty: Remove yosys+nextpnr INTERNAL_VREF constraint skip (now directly done in LiteX).	2022-02-14 10:45:29 +01:00
prog	Add JTAGbone support to Terasic DECA	2022-01-27 14:13:58 -08:00
targets	sqrl_acorn: Downgrade to SATA Gen1 for now (allow lower sys_clk_freq and enough for current tests).	2022-02-09 19:10:12 +01:00
tools	general: add SPDX License identifier to header and specify files are part of LiteX-Boards.	2020-08-23 15:00:17 +02:00
__init__.py	alinx_axu2gca: new board	2022-01-25 07:35:42 +01:00