144 lines
5.3 KiB
Python
144 lines
5.3 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# https://www.crowdsupply.com/fairwaves/xtrx
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk/Rst.
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("clk60", 0, Pins("C16"), IOStandard("LVCMOS25")),
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# Leds.
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("user_led", 0, Pins("N18"), IOStandard("LVCMOS25")),
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# PCIe.
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("pcie_x2", 0,
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Subsignal("rst_n", Pins("T3"), IOStandard("LVCMOS25"), Misc("PULLUP=TRUE")),
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Subsignal("clk_p", Pins("B8")),
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Subsignal("clk_n", Pins("A8")),
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Subsignal("rx_p", Pins("B6 B4")),
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Subsignal("rx_n", Pins("A6 A4")),
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Subsignal("tx_p", Pins("B2 D2")),
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Subsignal("tx_n", Pins("A2 D1")),
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),
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# SPIFlash.
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("flash_cs_n", 0, Pins("K19"), IOStandard("LVCMOS25")),
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("flash", 0,
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Subsignal("mosi", Pins("D18")),
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Subsignal("miso", Pins("D19")),
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Subsignal("wp", Pins("G18")),
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Subsignal("hold", Pins("F18")),
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IOStandard("LVCMOS25")
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),
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# I2C
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("i2c", 0,
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Subsignal("scl", Pins("M1"), Misc("PULLUP=True")),
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Subsignal("sda", Pins("N1"), Misc("PULLUP=True")),
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IOStandard("LVCMOS33"),
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),
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# GPS.
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("gps", 0,
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Subsignal("pps", Pins("P3"), Misc("PULLDOWN=True")),
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Subsignal("txd", Pins("N2"), Misc("PULLUP=True")),
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Subsignal("rxd", Pins("L1"), Misc("PULLUP=True")),
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IOStandard("LVCMOS33")
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),
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# AUX. (Split/Move/Rename?)
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("aux", 0,
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Subsignal("fpga_clk_vctcxo", Pins("N17"), Misc("PULLDOWN=True")),
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Subsignal("en_tcxo", Pins("R19"), Misc("PULLUP=True")),
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Subsignal("ext_clk", Pins("V17"), Misc("PULLDOWN=True")),
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Subsignal("en_gps", Pins("L18")),
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Subsignal("iovcc_sel", Pins("V19")),
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Subsignal("en_smsigio", Pins("D17")),
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IOStandard("LVCMOS25")
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),
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# RF-Switches / SKY13330, SKY13384.
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("rfswitches", 0,
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Subsignal("tx", Pins("P1"), Misc("PULLUP=True")),
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Subsignal("rx", Pins("K3 J3"), Misc("PULLUP=True")),
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IOStandard("LVCMOS33")
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),
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# RF-IC / LMS7002M.
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("rfic",
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# SPI / Control.
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Subsignal("saen", Pins("W13")),
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Subsignal("sdio", Pins("W16"), Misc("PULLDOWN=True")),
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Subsignal("sdo", Pins("W15"), Misc("PULLDOWN=True")),
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Subsignal("sclk", Pins("W14")),
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Subsignal("reset", Pins("U19")),
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Subsignal("gpwrdwn", Pins("W17")),
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Subsignal("rxen", Pins("W18")),
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Subsignal("txen", Pins("W19")),
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# Port1.
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Subsignal("diq1", Pins("J19 H17 G17 K17 H19 U16 J17 P19 U17 N19 V15 V16")),
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Subsignal("txnrx1", Pins("M19")),
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Subsignal("iqsel1", Pins("P17")),
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Subsignal("mclk1", Pins("L17")),
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Subsignal("fclk1", Pins("G19")),
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# Port2.
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Subsignal("diq2", Pins("W2 U2 V3 V4 V5 W7 V2 W4 U5 V8 U7 U8")),
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Subsignal("txnrx2", Pins("U4")),
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Subsignal("iqsel2", Pins("U3")),
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Subsignal("mclk2", Pins("W5")),
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Subsignal("fclk2", Pins("W6")),
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# IOStandard/Slew Rate.
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IOStandard("LVCMOS25"),
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Misc("SLEW=FAST"),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk60"
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default_clk_period = 1e9/60e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a50tcpg236-2", _io, toolchain="vivado")
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self.toolchain.bitstream_commands = [
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"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]",
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"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
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]
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self.toolchain.additional_commands = [
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# Non-Multiboot SPI-Flash bitstream generation.
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"write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin",
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# Multiboot SPI-Flash Operational bitstream generation.
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"set_property BITSTREAM.CONFIG.TIMER_CFG 0x0001fbd0 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]",
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"write_bitstream -force {build_name}_operational.bit ",
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"write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}_operational.bit\" -file {build_name}_operational.bin",
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# Multiboot SPI-Flash Fallback bitstream generation.
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"set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x00400000 [current_design]",
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"write_bitstream -force {build_name}_fallback.bit ",
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"write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}_fallback.bit\" -file {build_name}_fallback.bin"
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]
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a50t.bit")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk60", loose=True), 1e9/60e6)
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