108 lines
3.9 KiB
Python
108 lines
3.9 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019-2021 Antti Lukats <antti.lukats@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# http://trenz.org/max1000-info
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk12", 0, Pins("H6"), IOStandard("3.3-V LVTTL")),
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# Leds
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("user_led", 0, Pins("A8"), IOStandard("3.3-V LVTTL")),
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("user_led", 1, Pins("A9"), IOStandard("3.3-V LVTTL")),
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("user_led", 2, Pins("A11"), IOStandard("3.3-V LVTTL")),
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("user_led", 3, Pins("A10"), IOStandard("3.3-V LVTTL")),
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("user_led", 4, Pins("B10"), IOStandard("3.3-V LVTTL")),
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("user_led", 5, Pins("C9"), IOStandard("3.3-V LVTTL")),
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("user_led", 6, Pins("C10"), IOStandard("3.3-V LVTTL")),
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("user_led", 7, Pins("D8"), IOStandard("3.3-V LVTTL")),
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# Buttons
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("user_btn", 0, Pins("E6"), IOStandard("3.3-V LVTTL")),
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("user_btn", 1, Pins("E7"), IOStandard("3.3-V LVTTL")), # nConfig.
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("B4"), IOStandard("3.3-V LVTTL")),
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Subsignal("rx", Pins("A4"), IOStandard("3.3-V LVTTL"))
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),
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# SPI Flash
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("B3")),
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Subsignal("clk", Pins("A3")),
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Subsignal("dq", Pins("A2", "B2", "B9", "C4")),
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IOStandard("3.3-V LVTTL")
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),
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("spiflash", 0,
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Subsignal("cs_n", Pins("B3")),
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Subsignal("clk", Pins("A3")),
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Subsignal("mosi", Pins("A2")),
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Subsignal("miso", Pins("B2")),
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Subsignal("wp", Pins("B9")),
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Subsignal("hold", Pins("C4")),
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IOStandard("3.3-V LVTTL"),
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),
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# SDRAM
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("sdram_clock", 0, Pins("M9"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins(
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"K6 M5 N5 J8 N10 M11 N9 L10",
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"M13 N8 N4 M10")),
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Subsignal("ba", Pins("N6 K8")),
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Subsignal("cs_n", Pins("M4")),
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Subsignal("cke", Pins("M8")),
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Subsignal("ras_n", Pins("M7")),
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Subsignal("cas_n", Pins("N7")),
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Subsignal("we_n", Pins("K7")),
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Subsignal("dq", Pins(
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"D11 G10 F10 F9 E10 D9 G9 F8",
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"F13 E12 E13 D12 C12 B12 B13 A12")),
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Subsignal("dm", Pins("E9 F12")),
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IOStandard("3.3-V LVTTL")
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),
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# all IO not connected to peripherals mapped to MFIO
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# <- LEDS -> <- PMOD -> <- D0..D14, D11R, D12R -> <- AIN0..AIN7 -> JE [C O I S i1 i2]sw
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("bbio", 0, Pins("A8 A9 A11 A10 B10 C9 C10 D8 M3 L3 M2 M1 N3 N2 K2 K1 H8 K10 H5 H4 J1 J2 L12 J12 J13 K11 K12 J10 H10 H13 G12 B11 G13 E1 C2 C1 D1 E3 F1 E4 B1 E5 J6 J7 K5 L5 J5 L4 E6"),
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IOStandard("3.3-V LVTTL")),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk12"
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default_clk_period = 1e9/12e6
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def __init__(self):
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AlteraPlatform.__init__(self, "10M08SAU169C8G", _io)
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self.add_platform_command("set_global_assignment -name FAMILY \"MAX 10\"")
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self.add_platform_command("set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF")
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self.add_platform_command("set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE \"SINGLE IMAGE WITH ERAM\"")
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def create_programmer(self):
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return USBBlaster()
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6)
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# Generate PLL clock in STA
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self.toolchain.additional_sdc_commands.append("derive_pll_clocks")
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# Calculates clock uncertainties
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self.toolchain.additional_sdc_commands.append("derive_clock_uncertainty")
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