194 lines
8.5 KiB
Python
Executable File
194 lines
8.5 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Sergiu Mosanu <sm7ed@virginia.edu>
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# Copyright (c) 2020-2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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# To interface via the serial port use:
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# lxterm /dev/ttyUSBx --speed=115200
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import os
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import LiteXModule
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from litex_boards.platforms import xilinx_alveo_u280
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.interconnect.axi import *
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from litex.soc.interconnect.csr import *
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from litex.soc.cores.ram.xilinx_usp_hbm2 import USPHBM2
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MTA18ASF2G72PZ
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from litedram.phy import usddrphy
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from litepcie.phy.usppciephy import USPPCIEPHY
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from litepcie.software import generate_litepcie_software
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from litedram.common import *
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from litedram.frontend.axi import *
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from litescope import LiteScopeAnalyzer
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, ddram_channel, with_hbm):
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if with_hbm:
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self.cd_sys = ClockDomain()
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self.cd_hbm_ref = ClockDomain()
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self.cd_apb = ClockDomain()
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else: # ddr4
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_pll4x = ClockDomain()
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self.cd_idelay = ClockDomain()
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# # #
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if with_hbm:
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self.pll = pll = USMMCM(speedgrade=-2)
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pll.register_clkin(platform.request("sysclk", ddram_channel), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_hbm_ref, 100e6)
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pll.create_clkout(self.cd_apb, 100e6)
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platform.add_false_path_constraints(self.cd_sys.clk, self.cd_apb.clk)
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else: # ddr4
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self.pll = pll = USMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request("sysclk", ddram_channel), 100e6)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_idelay, 600e6) #, with_reset=False
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.specials += [
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Instance("BUFGCE_DIV",
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p_BUFGCE_DIVIDE=4,
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
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Instance("BUFGCE",
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
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# AsyncResetSynchronizer(self.cd_idelay, ~pll.locked),
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]
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self.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(150e6), ddram_channel=0, with_pcie=False, with_led_chaser=False, with_hbm=False, **kwargs):
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platform = xilinx_alveo_u280.Platform()
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if with_hbm:
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assert 225e6 <= sys_clk_freq <= 450e6
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq, ddram_channel, with_hbm)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alveo U280 (ES1)", **kwargs)
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# HBM / DRAM -------------------------------------------------------------------------------
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if with_hbm:
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# JTAGBone -----------------------------------------------------------------------------
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#self.add_jtagbone(chain=2) # Chain 1 already used by HBM2 debug probes.
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# Add HBM Core.
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self.hbm = hbm = ClockDomainsRenamer({"axi": "sys"})(USPHBM2(platform))
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# Get HBM .xci.
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os.system("wget https://github.com/litex-hub/litex-boards/files/6893157/hbm_0.xci.txt")
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os.makedirs("ip/hbm", exist_ok=True)
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os.system("mv hbm_0.xci.txt ip/hbm/hbm_0.xci")
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# Connect four of the HBM's AXI interfaces to the main bus of the SoC.
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for i in range(4):
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axi_hbm = hbm.axi[i]
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axi_lite_hbm = AXILiteInterface(data_width=256, address_width=33)
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self.submodules += AXILite2AXI(axi_lite_hbm, axi_hbm)
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self.bus.add_slave(f"hbm{i}", axi_lite_hbm, SoCRegion(origin=0x4000_0000 + 0x1000_0000*i, size=0x1000_0000)) # 256MB.
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# Link HBM2 channel 0 as main RAM
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self.bus.add_region("main_ram", SoCRegion(origin=0x4000_0000, size=0x1000_0000, linker=True)) # 256MB.
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else:
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# DDR4 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram", ddram_channel),
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memtype = "DDR4",
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cmd_latency = 1, # seems to work better with cmd_latency=1
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 600e6,
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is_rdimm = True)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
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size = 0x40000000,
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Firmware RAM (To ease initial LiteDRAM calibration support) --------------------------
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self.add_ram("firmware_ram", 0x20000000, 0x8000)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("gpio_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=xilinx_alveo_u280.Platform, description="LiteX SoC on Alveo U280")
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parser.add_target_argument("--sys-clk-freq", default=150e6, help="System clock frequency.") # HBM2 with 250MHz, DDR4 with 150MHz (1:4)
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parser.add_target_argument("--ddram-channel", default="0", help="DDRAM channel (0, 1, 2 or 3).") # also selects clk 0 or 1
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parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
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parser.add_target_argument("--driver", action="store_true", help="Generate PCIe driver.")
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parser.add_target_argument("--with-hbm", action="store_true", help="Use HBM2.")
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parser.add_target_argument("--with-analyzer", action="store_true", help="Enable Analyzer.")
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parser.add_target_argument("--with-led-chaser", action="store_true", help="Enable LED Chaser.")
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args = parser.parse_args()
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if args.with_hbm:
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args.sys_clk_freq = 250e6
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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ddram_channel = int(args.ddram_channel, 0),
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with_pcie = args.with_pcie,
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with_led_chaser = args.with_led_chaser,
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with_hbm = args.with_hbm,
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with_analyzer = args.with_analyzer,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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