Florent Kermarrec 184f41e61a sipeed_tang_nano: Use PLL and 48MHz sys_clk, switch to SoCMini, add UARTBone (at 1MBauds). ... Working correctly on hardware with updated CH552 firmware & patched litex_server...		2021-11-08 09:23:44 +01:00
..
platforms	sqrl_acorn: fix vivado cfgbvs and config_voltage warnings	2021-11-07 16:18:22 +01:00
prog	prog/openocd_butterstick: Set _CHIPNAME to ecp5 (for jtag_uart/jtag_bone).	2021-10-27 17:27:07 +02:00
targets	sipeed_tang_nano: Use PLL and 48MHz sys_clk, switch to SoCMini, add UARTBone (at 1MBauds).	2021-11-08 09:23:44 +01:00
tools	general: add SPDX License identifier to header and specify files are part of LiteX-Boards.	2020-08-23 15:00:17 +02:00
__init__.py	Add initial Fairwaves XTRX support (SoC with JTAG-UART and PCIe Gen2 X1).	2021-11-05 14:52:45 +01:00