226 lines
9.7 KiB
Python
Executable File
226 lines
9.7 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# Build/Use ----------------------------------------------------------------------------------------
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# Build/Load bitstream:
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# ./ocp_tap_timecard.py --uart-name=crossover --with-pcie --with-smas --build --driver --load (or --flash)
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#
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#.Build the kernel and load it:
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# cd build/<platform>/driver/kernel
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# make
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# sudo ./init.sh
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#
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# Test userspace utilities:
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# cd build/<platform>/driver/user
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# make
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# ./litepcie_util info
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# ./litepcie_util scratch_test
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# ./litepcie_util dma_test
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# ./litepcie_util uart_test
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import os
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import ocp_tap_timecard
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import stream
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.xadc import XADC
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from litex.soc.cores.dna import DNA
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from litedram.modules import MT41K256M16
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from litedram.phy import s7ddrphy
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_sys4x_dqs = ClockDomain()
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self.cd_idelay = ClockDomain()
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# Clk/Rst
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clk200 = platform.request("clk200")
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# PLL
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self.pll = pll = S7PLL()
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk200, 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC -----------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=100e6,
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with_led_chaser = True,
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with_pcie = False,
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with_smas = False,
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**kwargs):
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platform = ocp_tap_timecard.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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kwargs["uart_name"] = "crossover"
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on OCP-TAP TimeCard", **kwargs)
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# XADC -------------------------------------------------------------------------------------
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self.xadc = XADC()
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# DNA --------------------------------------------------------------------------------------
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self.dna = DNA()
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self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq
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)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
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data_width = 64,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1, address_width=64)
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# FIXME: Apply it to all targets (integrate it in LitePCIe?).
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platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
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platform.toolchain.pre_placement_commands.append("reset_property LOC [get_cells -hierarchical -filter {{NAME=~*gtp_channel.gtpe2_channel_i}}]")
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platform.toolchain.pre_placement_commands.append("set_property LOC GTPE2_CHANNEL_X0Y5 [get_cells -hierarchical -filter {{NAME=~*gtp_channel.gtpe2_channel_i}}]")
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# ICAP (For FPGA reload over PCIe).
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from litex.soc.cores.icap import ICAP
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self.icap = ICAP()
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self.icap.add_reload()
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self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
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# Flash (For SPIFlash update over PCIe).
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from litex.soc.cores.gpio import GPIOOut
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from litex.soc.cores.spi_flash import S7SPIFlash
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self.flash_cs_n = GPIOOut(platform.request("flash_cs_n"))
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self.flash = S7SPIFlash(platform.request("flash"), sys_clk_freq, 25e6)
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# SMAs -------------------------------------------------------------------------------------
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if with_smas:
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# TODO:
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# - Use IO primitives to increase IO freqs (up to 800Mz would be fine) and PCIe Gen2 X1
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# should be able to saturate it (~3.4Gbps of useful bandwidth).
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# - Allow IO freq configuration (through PLL/MMCM and/or dividers).
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class SMAIOs(LiteXModule):
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def __init__(self, pcie_data_width=64, io_data_width=4):
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# Endpoints.
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self.sink = stream.Endpoint([("data", pcie_data_width)])
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self.source = stream.Endpoint([("data", pcie_data_width)])
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# CSRs.
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self.control = CSRStorage(fields=[
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CSRField("in_en", size=io_data_width, description="Input enable control (1bit per SMA)."),
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CSRField("out_en", size=io_data_width, description="Output enable control (1bit per SMA)."),
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])
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self.output = CSRStorage(io_data_width, description="SMA Reg Output (1bit per SMA).")
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self.input = CSRStatus(io_data_width, description="SMA Reg Input (1bit per SMA).")
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# # #
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# SMA Pads.
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sma_pads = [platform.request("sma", i) for i in range(io_data_width)]
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# SMA Buffer Control.
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for i in range(io_data_width):
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self.sync += sma_pads[i].dat_in_en.eq( self.control.fields.in_en)
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self.sync += sma_pads[i].dat_out_en.eq(self.control.fields.in_en)
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# SMA TX Reg, allow direct (and slow...) control of SMA IOs.
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for i in range(io_data_width):
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self.sync += If(self.output.storage[i],
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sma_pads[i].dat_out.eq(1)
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)
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# SMA TX Data Pipeline.
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self.tx_converter = tx_converter = stream.Converter(pcie_data_width, io_data_width)
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self.comb += self.sink.connect(self.tx_converter.sink)
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self.comb += self.tx_converter.source.ready.eq(1)
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for i in range(io_data_width):
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self.sync += If(tx_converter.source.valid & tx_converter.source.data[i],
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sma_pads[i].dat_out.eq(1)
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)
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# SMA RX Reg, allow direct (and slow...) visualization of SMA IOs.
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for i in range(io_data_width):
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self.sync += self.input.status[i].eq(sma_pads[i].dat_in)
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# SMA RX Data Pipeline.
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self.rx_converter = stream.Converter(io_data_width, pcie_data_width)
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self.comb += self.rx_converter.sink.valid.eq(1)
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for i in range(io_data_width):
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self.sync += self.rx_converter.sink.data[i].eq(sma_pads[i].dat_in)
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self.comb += self.rx_converter.source.connect(self.source)
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self.smas = SMAIOs(pcie_data_width=64, io_data_width=4)
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self.comb += self.pcie_dma0.source.connect(self.smas.sink)
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self.comb += self.smas.source.connect(self.pcie_dma0.sink)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=ocp_tap_timecard.Platform, description="LiteX SoC on OCP-TAP TimeCard.")
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parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
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parser.add_target_argument("--with-smas", action="store_true", help="Enable SMAs support.")
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parser.add_target_argument("--driver", action="store_true", help="Generate PCIe driver.")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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with_pcie = args.with_pcie,
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with_smas = args.with_smas,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, builder.get_bitstream_filename(mode="flash"))
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if __name__ == "__main__":
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main()
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