95 lines
3.4 KiB
Python
95 lines
3.4 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# Board diagram/pinout:
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# http://www.fabienm.eu/flf/wp-content/uploads/2021/08/Tang-Nano-4K-specifications.jpg
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# http://www.fabienm.eu/flf/wp-content/uploads/2021/08/Tang-Nano-4K-GW1NSR-4C-FPGA-board-pinout-diagram.jpg
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.gowin.platform import GowinPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk27", 0, Pins("45"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("10"), IOStandard("LVCMOS33")),
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# Buttons.
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("user_btn", 0, Pins("14"), IOStandard("LVCMOS18")),
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("user_btn", 1, Pins("15"), IOStandard("LVCMOS18")),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("2"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("1"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("47"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("48"), IOStandard("LVCMOS33")),
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Subsignal("wp", Pins("8"), IOStandard("LVCMOS33")),
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Subsignal("hold", Pins("9"), IOStandard("LVCMOS33")),
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("2")),
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Subsignal("clk", Pins("1")),
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Subsignal("dq", Pins("48 47 8 9")),
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IOStandard("LVCMOS33")
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),
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# HyperRAM (embedded in SIP, requires specific IO naming).
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("O_hpram_ck", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_hpram_ck_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_hpram_cs_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_hpram_reset_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("IO_hpram_dq", 0, Pins(8), IOStandard("LVCMOS33")),
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("IO_hpram_rwds", 0, Pins(1), IOStandard("LVCMOS33")),
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# HDMI Out.
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("hdmi_out", 0,
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Subsignal("clk_p", Pins("28")),
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Subsignal("clk_n", Pins("27")),
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Subsignal("data0_p", Pins("30")),
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Subsignal("data0_n", Pins("29")),
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Subsignal("data1_p", Pins("32")),
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Subsignal("data1_n", Pins("31")),
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Subsignal("data2_p", Pins("35")),
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Subsignal("data2_n", Pins("34")),
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Misc("PULL_MODE=NONE"),
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Misc("DRIVE=3.5"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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["P6", "30 29 28 27 23 22 21 20 19 18 17 13 16 9 8 33 2 - - - - 15"],
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["P7", "31 32 34 35 10 39 40 41 42 43 47 48 1 46 44 - - 6 3 4 7 14"],
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(GowinPlatform):
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default_clk_name = "clk27"
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default_clk_period = 1e9/27e6
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def __init__(self):
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GowinPlatform.__init__(self, "GW1NSR-LV4CQN48PC7/I6", _io, _connectors, toolchain="gowin", devicename="GW1NSR-4C")
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self.toolchain.options["use_mode_as_gpio"] = 1
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self.toolchain.options["use_mspi_as_gpio"] = 1
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self.toolchain.options["use_done_as_gpio"] = 1
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def create_programmer(self):
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return OpenFPGALoader("tangnano4k")
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def do_finalize(self, fragment):
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GowinPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk27", loose=True), 1e9/27e6)
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