105 lines
4.1 KiB
Python
Executable File
105 lines
4.1 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2021 Greg Davill <greg.davill@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import sys
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import argparse
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from migen import *
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from litex_boards.platforms import butterstick
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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# CRG ---------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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# Clk / Rst
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clk30 = platform.request("clk30")
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rst_n = platform.request("user_btn", 0)
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk30)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst)
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pll.register_clkin(clk30, 30e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, revision="1.0", device="25F", sys_clk_freq=int(60e6), toolchain="trellis", with_led_chaser=True, **kwargs):
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platform = butterstick.Platform(revision=revision, device=device ,toolchain=toolchain)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on ButterStick",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.comb += platform.request("user_led_color").eq(0b010) # Blue.
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on ButterStick")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--toolchain", default="trellis", help="FPGA use, trellis (default) or diamond")
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parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)")
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parser.add_argument("--revision", default="1.0", help="Board Revision: 1.0 (default)")
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parser.add_argument("--device", default="85F", help="ECP5 device (default: 85F)")
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builder_args(parser)
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soc_core_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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toolchain = args.toolchain,
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revision = args.revision,
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device = args.device,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
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builder.build(**builder_kargs, run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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