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Sylvain Munaut 2264df8a0a adi_adrv2crr_fmc: Speedgrade of the PLL is -2 
Speedgrade of the chip was updated in a previous commit, but
I forgot to update the PLL too

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2024-02-05 11:42:14 +01:00
..
platforms sipeed_tang_mega_138k: Added PCIe reset and other pins from sipeed documentation 2024-01-13 04:38:54 -03:00
prog prog/openocd_ecpix5.cfg: refresh/fix 2023-12-13 18:34:02 +01:00
targets adi_adrv2crr_fmc: Speedgrade of the PLL is -2 2024-02-05 11:42:14 +01:00
__init__.py