111 lines
4.1 KiB
Python
Executable File
111 lines
4.1 KiB
Python
Executable File
#!/usr/bin/env python3
|
|
import argparse
|
|
|
|
from migen import *
|
|
from migen.genlib.io import CRG
|
|
|
|
from litex_boards.platforms import zcu104
|
|
|
|
from litex.soc.cores.clock import *
|
|
from litex.soc.integration.soc_sdram import *
|
|
from litex.soc.integration.builder import *
|
|
|
|
from litedram.modules import KVR21SE15S84
|
|
from litedram.phy import usddrphy
|
|
|
|
# CRG ----------------------------------------------------------------------------------------------
|
|
|
|
class _CRG(Module):
|
|
def __init__(self, platform, sys_clk_freq):
|
|
self.clock_domains.cd_sys = ClockDomain()
|
|
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
|
|
self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
|
|
self.clock_domains.cd_clk500 = ClockDomain()
|
|
self.clock_domains.cd_ic = ClockDomain()
|
|
|
|
self.submodules.pll = pll = USMMCM(speedgrade=-2)
|
|
pll.register_clkin(platform.request("clk125"), 125e6)
|
|
|
|
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
|
|
pll.create_clkout(self.cd_clk500, 500e6, with_reset=False)
|
|
|
|
self.specials += [
|
|
Instance("BUFGCE_DIV", name="main_bufgce_div",
|
|
p_BUFGCE_DIVIDE=4,
|
|
i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
|
|
Instance("BUFGCE", name="main_bufgce",
|
|
i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
|
|
AsyncResetSynchronizer(self.cd_clk500, ~pll.locked),
|
|
]
|
|
|
|
ic_reset_counter = Signal(max=64, reset=63)
|
|
ic_reset = Signal(reset=1)
|
|
self.sync.clk500 += \
|
|
If(ic_reset_counter != 0,
|
|
ic_reset_counter.eq(ic_reset_counter - 1)
|
|
).Else(
|
|
ic_reset.eq(0)
|
|
)
|
|
ic_rdy = Signal()
|
|
ic_rdy_counter = Signal(max=64, reset=63)
|
|
self.cd_sys.rst.reset = 1
|
|
self.comb += self.cd_ic.clk.eq(self.cd_sys.clk)
|
|
self.sync.ic += [
|
|
If(ic_rdy,
|
|
If(ic_rdy_counter != 0,
|
|
ic_rdy_counter.eq(ic_rdy_counter - 1)
|
|
).Else(
|
|
self.cd_sys.rst.eq(0)
|
|
)
|
|
)
|
|
]
|
|
self.specials += [
|
|
Instance("IDELAYCTRL", p_SIM_DEVICE="ULTRASCALE",
|
|
i_REFCLK=ClockSignal("clk500"), i_RST=ic_reset,
|
|
o_RDY=ic_rdy),
|
|
AsyncResetSynchronizer(self.cd_ic, ic_reset)
|
|
]
|
|
|
|
# BaseSoC ------------------------------------------------------------------------------------------
|
|
|
|
class BaseSoC(SoCSDRAM):
|
|
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
|
|
platform = zcu104.Platform()
|
|
|
|
# SoCSDRAM ---------------------------------------------------------------------------------
|
|
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
|
|
|
|
# CRG --------------------------------------------------------------------------------------
|
|
self.submodules.crg = _CRG(platform, sys_clk_freq)
|
|
|
|
# DDR4 SDRAM -------------------------------------------------------------------------------
|
|
if not self.integrated_main_ram_size:
|
|
self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
|
|
memtype = "DDR4",
|
|
sim_device = "ULTRASCALE_PLUS",
|
|
iodelay_clk_freq = 500e6,
|
|
cmd_latency = 1,
|
|
sys_clk_freq = sys_clk_freq)
|
|
self.add_csr("ddrphy")
|
|
self.add_constant("USDDRPHY", None)
|
|
sdram_module = KVR21SE15S84(sys_clk_freq, "1:4")
|
|
self.register_sdram(self.ddrphy,
|
|
geom_settings = sdram_module.geom_settings,
|
|
timing_settings = sdram_module.timing_settings)
|
|
|
|
# Build --------------------------------------------------------------------------------------------
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(description="LiteX SoC on ZCU104")
|
|
builder_args(parser)
|
|
soc_sdram_args(parser)
|
|
args = parser.parse_args()
|
|
|
|
soc = BaseSoC(**soc_sdram_argdict(args))
|
|
builder = Builder(soc, **builder_argdict(args))
|
|
builder.build()
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main()
|