149 lines
6.3 KiB
Python
Executable File
149 lines
6.3 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 David Corrigan <davidcorrigan714@gmail.com>
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# Copyright (c) 2020 Alan Green <avg@google.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import *
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from litex_boards.platforms import lattice_crosslink_nx_evn
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from litex.soc.cores.ram import NXLRAM
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from litex.soc.cores.clock import NXPLL
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from litex.build.io import CRG
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from litex.build.generic_platform import *
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_por = ClockDomain()
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self.cd_sys = ClockDomain()
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# Built in OSC
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self.hf_clk = NXOSCA()
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hf_clk_freq = 25e6
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self.hf_clk.create_hf_clk(self.cd_por, hf_clk_freq)
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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self.rst_n = platform.request("gsrn")
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self.specials += AsyncResetSynchronizer(self.cd_por, ~self.rst_n)
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# PLL
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self.sys_pll = sys_pll = NXPLL(platform=platform, create_output_port_clocks=True)
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self.comb += sys_pll.reset.eq(self.rst)
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sys_pll.register_clkin(self.cd_por.clk, hf_clk_freq)
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sys_pll.create_clkout(self.cd_sys, sys_clk_freq)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~self.sys_pll.locked | ~por_done )
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {
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"rom" : 0x00000000,
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"sram" : 0x40000000,
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"main_ram" : 0x60000000,
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"csr" : 0xf0000000,
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}
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def __init__(self, sys_clk_freq=75e6, device="LIFCL-40-9BG400C", toolchain="radiant",
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with_led_chaser = True,
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with_spi_flash = False,
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with_uartbone = False,
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**kwargs):
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platform = lattice_crosslink_nx_evn.Platform(device=device, toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore -----------------------------------------_----------------------------------------
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# Disable Integrated SRAM since we want to instantiate LRAM specifically for it
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kwargs["integrated_sram_size"] = 0
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# Make serial_pmods available
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platform.add_extension(lattice_crosslink_nx_evn.serial_pmods)
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Crosslink-NX Evaluation Board", **kwargs)
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# 128KB LRAM (used as SRAM) ---------------------------------------------------------------
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self.spram = NXLRAM(32, 64*kB)
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self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=16*kB))
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self.main_ram = NXLRAM(32, 64*kB)
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self.bus.add_slave("main_ram", self.main_ram.bus, SoCRegion(origin=self.mem_map["main_ram"], size=64*kB))
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = Cat(*[platform.request("user_led", i) for i in range(14)]),
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sys_clk_freq = sys_clk_freq)
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# UARTBone ---------------------------------------------------------------------------------
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if with_uartbone:
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self.add_uartbone()
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import MX25L12833F
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x", clk_freq=100_000, module=MX25L12833F(Codes.READ_4_4_4), with_master=True)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=lattice_crosslink_nx_evn.Platform, description="LiteX SoC on Crosslink-NX Eval Board.")
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parser.add_target_argument("--device", default="LIFCL-40-9BG400C", help="FPGA device (LIFCL-40-9BG400C, LIFCL-40-8BG400CES, or LIFCL-40-8BG400CES2).")
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parser.add_target_argument("--sys-clk-freq", default=75e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--serial", default="serial", help="UART Pins (serial (requires R15 and R17 to be soldered) or serial_pmod[0-2]).")
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parser.add_target_argument("--programmer", default="radiant", help="Programmer (radiant or ecpprog).")
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parser.add_target_argument("--address", default=0x0, help="Flash address to program bitstream at.")
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parser.add_target_argument("--prog-target", default="direct", help="Programming Target (direct or flash).")
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parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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parser.add_target_argument("--with-uartbone", action="store_true", help="Add UartBone on 1st serial.")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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device = args.device,
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toolchain = args.toolchain,
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with_spi_flash = args.with_spi_flash,
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with_uartbone = args.with_uartbone,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer(args.prog_target, args.programmer)
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if args.programmer == "ecpprog" and args.prog_target == "flash":
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prog.flash(args.address, builder.get_bitstream_filename(mode="sram"))
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else:
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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