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https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
99e2f04ee5
Collect --with-ethernet/--with-etherbone, --with-spi-sdcard/--with-sdcard, etc. into ArgumentParser.add_mutually_exclusive_group()s. That way, we get pretty --help output, and appropriate error messages if somebody tries to ask for something that doesn't make sense.
112 lines
4.8 KiB
Python
Executable file
112 lines
4.8 KiB
Python
Executable file
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import pano_logic_g2
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from liteeth.phy import LiteEthPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, clk_freq, with_ethernet=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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if not with_ethernet:
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# Take Ethernet PHY out of reset to enable 125MHz on clk125 (25MHz otherwise).
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# See https://github.com/tomverbeure/panologic-g2#fpga-external-clocking-architecture
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self.comb += platform.request("eth_rst_n").eq(1)
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self.submodules.pll = pll = S6PLL(speedgrade=-2)
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self.comb += pll.reset.eq(~platform.request("user_btn_n") | self.rst)
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pll.register_clkin(platform.request("clk125"), 125e6)
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pll.create_clkout(self.cd_sys, clk_freq)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, revision, sys_clk_freq=int(50e6), with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", **kwargs):
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platform = pano_logic_g2.Platform(revision=revision)
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if with_etherbone:
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sys_clk_freq = int(125e6)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Pano Logic G2",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet=with_ethernet or with_etherbone)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHY(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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clk_freq = sys_clk_freq,
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with_hw_init_reset = False)
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self.add_csr("ethphy")
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Pano Logic G2")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--revision", default="c", help="Board revision c (default) or b")
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parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
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ethopts = parser.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
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parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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revision = args.revision,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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