130 lines
5.0 KiB
Python
Executable File
130 lines
5.0 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import argparse
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import subprocess
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from migen import *
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from litex_boards.platforms import digilent_arty_z7
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from litex.build import tools
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from litex.build.xilinx import common as xil_common
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.interconnect import axi
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, use_ps7_clk=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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if use_ps7_clk:
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self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
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self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
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else:
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request(platform.default_clk_name), platform.default_clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# Ignore sys_clk to pll.clkin path created by SoC's rst.
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, variant="z7-20", toolchain="vivado", sys_clk_freq=int(125e6),
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with_led_chaser=True, **kwargs):
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platform = digilent_arty_z7.Platform(variant=variant, toolchain=toolchain)
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if kwargs.get("cpu_type", None) == "zynq7000":
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kwargs['integrated_sram_size'] = 0
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kwargs['with_uart'] = False
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self.mem_map = {
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'csr': 0x4000_0000, # Zynq GP0 default
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}
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Arty Z7",
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**kwargs)
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# Zynq7000 Integration ---------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "zynq7000":
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assert toolchain == "vivado", ' not tested / specific vivado cmds'
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preset_name = "arty_z7_20.tcl" if variant == "z7-20" else "arty_z7_10.tcl"
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os.system("wget http://kmf2.trabucayre.com/" + preset_name)
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self.cpu.set_ps7(preset=preset_name)
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# Connect AXI GP0 to the SoC
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wb_gp0 = wishbone.Interface()
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self.submodules += axi.AXI2Wishbone(
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axi = self.cpu.add_axi_gp_master(),
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wishbone = wb_gp0,
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base_address = self.mem_map['csr'])
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self.add_wb_master(wb_gp0)
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use_ps7_clk = True
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else:
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use_ps7_clk = False
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Arty Z7")
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parser.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado, symbiflow or yosys+nextpnr).")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--variant", default="z7-20", help="Board variant (z7-20 or z7-10).")
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parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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parser.set_defaults(cpu_type="zynq7000")
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args = parser.parse_args()
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soc = BaseSoC(
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variant = args.variant,
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toolchain = args.toolchain,
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sys_clk_freq=int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
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builder.build(**builder_kwargs, run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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