140 lines
5.9 KiB
Python
Executable File
140 lines
5.9 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2019 Sean Cross <sean@xobs.io>
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# This file is Copyright (c) 2018 David Shah <dave@ds0.me>
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# This file is Copyright (c) 2020 Piotr Esden-Tempski <piotr@esden.net>
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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# The iCEBreaker is the first open source iCE40 FPGA development board designed for teachers and
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# students: https://www.crowdsupply.com/1bitsquared/icebreaker-fpga
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# This target file provides a minimal LiteX SoC for the iCEBreaker with a CPU, its ROM (in SPI Flash),
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# its SRAM, close to the others LiteX targets. A more complete example of LiteX SoC for the iCEBreaker
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# with more features, examples to run C/Rust code on the RISC-V CPU and documentation can be found
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# at: https://github.com/icebreaker-fpga/icebreaker-litex-examples
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import icebreaker
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from litex.soc.cores.up5kspram import Up5kSPRAM
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from litex.soc.cores.spi_flash import SpiFlash
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from litex.soc.cores.clock import iCE40PLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_por = ClockDomain()
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# # #
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# Clocking
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clk12 = platform.request("clk12")
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rst_n = platform.request("user_btn_n")
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if sys_clk_freq == 12e6:
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self.comb += self.cd_sys.clk.eq(clk12)
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else:
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self.submodules.pll = pll = iCE40PLL(primitive="SB_PLL40_PAD")
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pll.register_clkin(clk12, 12e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
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# Power On Reset
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por_cycles = 4096
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por_counter = Signal(log2_int(por_cycles), reset=por_cycles-1)
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self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
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platform.add_period_constraint(self.cd_por.clk, 1e9/sys_clk_freq)
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self.sync.por += If(por_counter != 0, por_counter.eq(por_counter - 1))
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self.specials += AsyncResetSynchronizer(self.cd_por, ~rst_n)
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self.specials += AsyncResetSynchronizer(self.cd_sys, (por_counter != 0))
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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SoCCore.mem_map = {
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"sram": 0x10000000,
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"spiflash": 0x20000000,
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"csr": 0xf0000000,
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}
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def __init__(self, bios_flash_offset, **kwargs):
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sys_clk_freq = int(24e6)
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platform = icebreaker.Platform()
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# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
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kwargs["integrated_sram_size"] = 0
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kwargs["integrated_rom_size"] = 0
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# Set CPU variant / reset address
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kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
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self.submodules.spram = Up5kSPRAM(size=64*kB)
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self.register_mem("sram", self.mem_map["sram"], self.spram.bus, 64*kB)
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# SPI Flash --------------------------------------------------------------------------------
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self.submodules.spiflash = SpiFlash(platform.request("spiflash4x"), dummy=6, endianness="little")
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self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=16*mB)
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self.add_csr("spiflash")
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# Add ROM linker region --------------------------------------------------------------------
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self.add_memory_region("rom", self.mem_map["spiflash"] + bios_flash_offset, 32*kB, type="cached+linker")
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# Leds -------------------------------------------------------------------------------------
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counter = Signal(32)
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self.sync += counter.eq(counter + 1)
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self.comb += platform.request("user_ledr_n").eq(counter[26])
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self.comb += platform.request("user_ledg_n").eq(~counter[26])
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# Flash --------------------------------------------------------------------------------------------
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def flash(bios_flash_offset):
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from litex.build.lattice.programmer import IceStormProgrammer
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prog = IceStormProgrammer()
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prog.flash(bios_flash_offset, "soc_basesoc_icebreaker/software/bios/bios.bin")
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prog.flash(0x00000000, "soc_basesoc_icebreaker/gateware/top.bin")
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exit()
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--bios-flash-offset", default=0x40000, help="BIOS offset in SPI Flash")
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parser.add_argument("--flash", action="store_true", help="Flash Bitstream")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(args.bios_flash_offset, **soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bin"))
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if args.flash:
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flash(args.bios_flash_offset)
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if __name__ == "__main__":
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main()
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