119 lines
3.5 KiB
Python
119 lines
3.5 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Primesh Pinto <primeshp@gmailcom>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk100", 0, Pins("H4"), IOStandard("LVCMOS33")),
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("rst_n", 0, Pins("D14"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("J1"), IOStandard("LVCMOS33")), # Green.
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("user_led", 1, Pins("A13"), IOStandard("LVCMOS33")), # Red.
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# RGB Leds (2 X SK6805 Leds)
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("rgb", 0, Pins("N11"),IOStandard("LVCMOS33")),
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# Buttons
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("user_btn", 0, Pins("C3"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("M4"), IOStandard("LVCMOS33")),
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# Mini HDMI
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("hdmi", 0,
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Subsignal("clk_p", Pins("G4"),IOStandard("LVCMOS33")),
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Subsignal("clk_n", Pins("F4"),IOStandard("LVCMOS33")),
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Subsignal("data0_p", Pins("G1"),IOStandard("LVCMOS33")),
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Subsignal("data0_n", Pins("F1"),IOStandard("LVCMOS33")),
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Subsignal("data1_p", Pins("E2"),IOStandard("LVCMOS33")),
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Subsignal("data1_n", Pins("D2"),IOStandard("LVCMOS33")),
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Subsignal("data2_p", Pins("D1"),IOStandard("LVCMOS33")),
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Subsignal("data2_n", Pins("C1"),IOStandard("LVCMOS33")),
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Subsignal("scl", Pins("F3"),IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("F2"),IOStandard("LVCMOS33")),
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Subsignal("hpd", Pins("D4"),IOStandard("LVCMOS33")),
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Subsignal("cec", Pins("E4"),IOStandard("LVCMOS33"))
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),
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# MIPI (Untested)
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("mipi", 0,
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Subsignal("clkp", Pins("G11"), IOStandard("MIPI_DPHY")),
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Subsignal("clkn", Pins("F11"), IOStandard("LVCMOS12H")),
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Subsignal("dp", Pins("J11 P10"), IOStandard("MIPI_DPHY")),
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Subsignal("dn", Pins("J12 P11"), IOStandard("LVCMOS12H")),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("j10", {
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"j10_0" : "N14",
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"j10_1" : "M14",
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"j10_2" : "C4",
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"j10_3" : "B13",
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"j10_4" : "N10",
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"j10_5" : "M10",
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"j10_6" : "B14",
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"j10_7" : "D3",
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"j10_8" : "P5",
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"j10_9" : "E11",
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}
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),
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("digital_d2",{
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"d2_0" : "A10",
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"d2_1" : "B6",
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}),
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("i2c", "P12 P13"), # SCL, SDA
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("ar_io", {
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# Outer Digital Header
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"d0" : "A12",
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"d1" : "C12",
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"d2" : "A10",
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"d3" : "B6",
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"d4" : "A5",
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"d5" : "B5",
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"d6" : "A4",
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"d7" : "A3",
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"d8" : "B3",
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"d9" : "A2",
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"d10" : "B2",
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"d11" : "B1",
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"d12" : "H1",
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"d13" : "H2",
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# Outer Analog Header as Digital IO
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"a0" : "F5",
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"a1" : "D8",
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"a2" : "C7",
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"a3" : "E7",
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"a4" : "D7",
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"a5" : "D5",
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} )
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, toolchain="vivado"):
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XilinxPlatform.__init__(self, "xc7s15-ftgb196", _io, _connectors, toolchain=toolchain)
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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