257 lines
8.2 KiB
Python
257 lines
8.2 KiB
Python
# This file is Copyright (c) 2015 Yann Sionneau <yann@sionneau.net>
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# This file is Copyright (c) 2015 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2018 William D. Jones <thor0505@comcast.net>
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# This file is Copyright (c) 2018 Caleb Jamison <cbjamo@gmail.com>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("user_led", 0, Pins("H5"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("J5"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("T9"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("T10"), IOStandard("LVCMOS33")),
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("rgb_led", 0,
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Subsignal("r", Pins("G6")),
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Subsignal("g", Pins("F6")),
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Subsignal("b", Pins("E1")),
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IOStandard("LVCMOS33"),
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),
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("rgb_led", 1,
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Subsignal("r", Pins("G3")),
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Subsignal("g", Pins("J4")),
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Subsignal("b", Pins("G4")),
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IOStandard("LVCMOS33"),
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),
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("rgb_led", 2,
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Subsignal("r", Pins("J3")),
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Subsignal("g", Pins("J2")),
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Subsignal("b", Pins("H4")),
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IOStandard("LVCMOS33"),
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),
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("rgb_led", 3,
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Subsignal("r", Pins("K1")),
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Subsignal("g", Pins("H6")),
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Subsignal("b", Pins("K2")),
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IOStandard("LVCMOS33"),
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),
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("user_sw", 0, Pins("A8"), IOStandard("LVCMOS33")),
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("user_sw", 1, Pins("C11"), IOStandard("LVCMOS33")),
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("user_sw", 2, Pins("C10"), IOStandard("LVCMOS33")),
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("user_sw", 3, Pins("A10"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("D9"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("C9"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("B9"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("B8"), IOStandard("LVCMOS33")),
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("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("C2"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("D10")),
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Subsignal("rx", Pins("A9")),
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IOStandard("LVCMOS33")
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),
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("spi", 0,
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Subsignal("clk", Pins("F1")),
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Subsignal("cs_n", Pins("C1")),
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Subsignal("mosi", Pins("H1")),
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Subsignal("miso", Pins("G1")),
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IOStandard("LVCMOS33"),
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),
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("i2c", 0,
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Subsignal("scl", Pins("L18")),
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Subsignal("sda", Pins("M18")),
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Subsignal("scl_pup", Pins("A14")),
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Subsignal("sda_pup", Pins("A13")),
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IOStandard("LVCMOS33"),
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),
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("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("L13")),
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Subsignal("dq", Pins("K17", "K18", "L14", "M14")),
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IOStandard("LVCMOS33")
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),
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("spiflash", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("L13")),
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Subsignal("mosi", Pins("K17")),
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Subsignal("miso", Pins("K18")),
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Subsignal("wp", Pins("L14")),
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Subsignal("hold", Pins("M14")),
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IOStandard("LVCMOS33"),
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),
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("ddram", 0,
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Subsignal("a", Pins(
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"R2 M6 N4 T1 N6 R7 V6 U7",
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"R8 V7 R6 U6 T6 T8"),
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IOStandard("SSTL135")),
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Subsignal("ba", Pins("R1 P4 P2"), IOStandard("SSTL135")),
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Subsignal("ras_n", Pins("P3"), IOStandard("SSTL135")),
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Subsignal("cas_n", Pins("M4"), IOStandard("SSTL135")),
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Subsignal("we_n", Pins("P5"), IOStandard("SSTL135")),
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Subsignal("cs_n", Pins("U8"), IOStandard("SSTL135")),
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Subsignal("dm", Pins("L1 U1"), IOStandard("SSTL135")),
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Subsignal("dq", Pins(
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"K5 L3 K3 L6 M3 M1 L4 M2",
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"V4 T5 U4 V5 V1 T3 U3 R3"),
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IOStandard("SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins("N2 U2"), IOStandard("DIFF_SSTL135")),
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Subsignal("dqs_n", Pins("N1 V2"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_p", Pins("U9"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_n", Pins("V9"), IOStandard("DIFF_SSTL135")),
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Subsignal("cke", Pins("N5"), IOStandard("SSTL135")),
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Subsignal("odt", Pins("R5"), IOStandard("SSTL135")),
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Subsignal("reset_n", Pins("K6"), IOStandard("SSTL135")),
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Misc("SLEW=FAST"),
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),
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("eth_ref_clk", 0, Pins("G18"), IOStandard("LVCMOS33")),
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("eth_clocks", 0,
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Subsignal("tx", Pins("H16")),
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Subsignal("rx", Pins("F15")),
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IOStandard("LVCMOS33"),
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),
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("eth", 0,
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Subsignal("rst_n", Pins("C16")),
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Subsignal("mdio", Pins("K13")),
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Subsignal("mdc", Pins("F16")),
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Subsignal("rx_dv", Pins("G16")),
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Subsignal("rx_er", Pins("C17")),
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Subsignal("rx_data", Pins("D18 E17 E18 G17")),
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Subsignal("tx_en", Pins("H15")),
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Subsignal("tx_data", Pins("H14 J14 J13 H17")),
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Subsignal("col", Pins("D17")),
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Subsignal("crs", Pins("G14")),
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IOStandard("LVCMOS33"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("pmoda", "G13 B11 A11 D12 D13 B18 A18 K16"),
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("pmodb", "E15 E16 D15 C15 J17 J18 K15 J15"),
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("pmodc", "U12 V12 V10 V11 U14 V14 T13 U13"),
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("pmodd", "D4 D3 F4 F3 E2 D2 H2 G2"),
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("ck_io", {
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# Outer Digital Header
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"ck_io0" : "V15",
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"ck_io1" : "U16",
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"ck_io2" : "P14",
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"ck_io3" : "T11",
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"ck_io4" : "R12",
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"ck_io5" : "T14",
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"ck_io6" : "T15",
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"ck_io7" : "T16",
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"ck_io8" : "N15",
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"ck_io9" : "M16",
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"ck_io10" : "V17",
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"ck_io11" : "U18",
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"ck_io12" : "R17",
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"ck_io13" : "P17",
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# Inner Digital Header
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"ck_io26" : "U11",
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"ck_io27" : "V16",
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"ck_io28" : "M13",
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"ck_io29" : "R10",
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"ck_io30" : "R11",
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"ck_io31" : "R13",
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"ck_io32" : "R15",
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"ck_io33" : "P15",
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"ck_io34" : "R16",
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"ck_io35" : "N16",
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"ck_io36" : "N14",
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"ck_io37" : "U17",
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"ck_io38" : "T18",
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"ck_io39" : "R18",
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"ck_io40" : "P18",
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"ck_io41" : "N17",
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# Outer Analog Header as Digital IO
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"ck_a0" : "F5",
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"ck_a1" : "D8",
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"ck_a2" : "C7",
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"ck_a3" : "E7",
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"ck_a4" : "D7",
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"ck_a5" : "D5",
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# Inner Analog Header as Digital IO
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"ck_io20" : "B7",
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"ck_io21" : "B6",
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"ck_io22" : "E6",
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"ck_io23" : "E5",
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"ck_io24" : "A4",
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"ck_io25" : "A3",
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} ),
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("XADC", {
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# Outer Analog Header
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"vaux4_n" : "C5",
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"vaux4_p" : "C6",
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"vaux5_n" : "A5",
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"vaux5_p" : "A6",
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"vaux6_n" : "B4",
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"vaux6_p" : "C4",
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"vaux7_n" : "A1",
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"vaux7_p" : "B1",
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"vaux15_n" : "B2",
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"vaux15_p" : "B3",
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"vaux0_n" : "C14",
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"vaux0_p" : "D14",
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# Inner Analog Header
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"vaux12_n" : "B7",
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"vaux12_p" : "B6",
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"vaux13_n" : "E6",
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"vaux13_p" : "E5",
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"vaux14_n" : "A4",
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"vaux14_p" : "A3",
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# Power Measurements
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"vsnsuv_n" : "B17",
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"vsnsuv_p" : "B16",
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"vsns5v0_n" : "B12",
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"vsns5v0_p" : "C12",
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"isns5v0_n" : "F14",
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"isns5v0_n" : "F13",
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"isns0v95_n" : "A16",
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"isns0v95_n" : "A15",
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} ),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 10.0
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def __init__(self, variant="a7-35"):
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device = {
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"a7-35": "xc7a35ticsg324-1L",
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"a7-100": "xc7a100tcsg324-1"
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}[variant]
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XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
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def create_programmer(self):
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return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
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