119 lines
4.9 KiB
Python
119 lines
4.9 KiB
Python
# This file is Copyright (c) 2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("user_led", 0, Pins("H17"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("K15"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("J13"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("N14"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("R18"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("V17"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("U17"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("U16"), IOStandard("LVCMOS33")),
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("user_led", 8, Pins("V16"), IOStandard("LVCMOS33")),
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("user_led", 9, Pins("T15"), IOStandard("LVCMOS33")),
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("user_led", 10, Pins("U14"), IOStandard("LVCMOS33")),
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("user_led", 11, Pins("T16"), IOStandard("LVCMOS33")),
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("user_led", 12, Pins("V15"), IOStandard("LVCMOS33")),
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("user_led", 13, Pins("V14"), IOStandard("LVCMOS33")),
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("user_led", 14, Pins("V12"), IOStandard("LVCMOS33")),
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("user_led", 15, Pins("V11"), IOStandard("LVCMOS33")),
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("user_sw", 0, Pins("J15"), IOStandard("LVCMOS33")),
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("user_sw", 1, Pins("L16"), IOStandard("LVCMOS33")),
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("user_sw", 2, Pins("M13"), IOStandard("LVCMOS33")),
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("user_sw", 3, Pins("R15"), IOStandard("LVCMOS33")),
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("user_sw", 4, Pins("R17"), IOStandard("LVCMOS33")),
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("user_sw", 5, Pins("T18"), IOStandard("LVCMOS33")),
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("user_sw", 6, Pins("U18"), IOStandard("LVCMOS33")),
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("user_sw", 7, Pins("R13"), IOStandard("LVCMOS33")),
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("user_sw", 8, Pins("T8"), IOStandard("LVCMOS33")),
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("user_sw", 9, Pins("U8"), IOStandard("LVCMOS33")),
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("user_sw", 10, Pins("R16"), IOStandard("LVCMOS33")),
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("user_sw", 11, Pins("T13"), IOStandard("LVCMOS33")),
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("user_sw", 12, Pins("H6"), IOStandard("LVCMOS33")),
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("user_sw", 13, Pins("U12"), IOStandard("LVCMOS33")),
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("user_sw", 14, Pins("U11"), IOStandard("LVCMOS33")),
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("user_sw", 15, Pins("V10"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("N17"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("P18"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("P17"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("M17"), IOStandard("LVCMOS33")),
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("user_btn", 4, Pins("M18"), IOStandard("LVCMOS33")),
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("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("C12"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("D4")),
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Subsignal("rx", Pins("C4")),
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IOStandard("LVCMOS33"),
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),
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("ddram", 0,
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Subsignal("a", Pins(
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"M4 P4 M6 T1 L3 P5 M2 N1",
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"L4 N5 R2 K5 N6"),
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IOStandard("SSTL18_II")),
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Subsignal("ba", Pins("P2 P3 R1"), IOStandard("SSTL18_II")),
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Subsignal("ras_n", Pins("N4"), IOStandard("SSTL18_II")),
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Subsignal("cas_n", Pins("L1"), IOStandard("SSTL18_II")),
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Subsignal("we_n", Pins("N2"), IOStandard("SSTL18_II")),
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Subsignal("dm", Pins("T6 U1"), IOStandard("SSTL18_II")),
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Subsignal("dq", Pins(
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"R7 V6 R8 U7 V7 R6 U6 R5",
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"T5 U3 V5 U4 V4 T4 V1 T3"),
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IOStandard("SSTL18_II"),
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Misc("IN_TERM=UNTUNED_SPLIT_50")),
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Subsignal("dqs_p", Pins("U9 U2"), IOStandard("DIFF_SSTL18_II")),
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Subsignal("dqs_n", Pins("V9 V2"), IOStandard("DIFF_SSTL18_II")),
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Subsignal("clk_p", Pins("L6"), IOStandard("DIFF_SSTL18_II")),
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Subsignal("clk_n", Pins("L5"), IOStandard("DIFF_SSTL18_II")),
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Subsignal("cke", Pins("M1"), IOStandard("SSTL18_II")),
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Subsignal("odt", Pins("M3"), IOStandard("SSTL18_II")),
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Subsignal("cs_n", Pins("K6"), IOStandard("SSTL18_II")),
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Misc("SLEW=FAST"),
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),
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("eth_clocks", 0,
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Subsignal("ref_clk", Pins("D5")),
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IOStandard("LVCMOS33"),
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),
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("eth", 0,
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Subsignal("rst_n", Pins("B3")),
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Subsignal("rx_data", Pins("C11 D10")),
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Subsignal("crs_dv", Pins("D9")),
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Subsignal("tx_en", Pins("B9")),
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Subsignal("tx_data", Pins("A10 A8")),
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Subsignal("mdc", Pins("C9")),
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Subsignal("mdio", Pins("A9")),
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Subsignal("rx_er", Pins("C10")),
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Subsignal("int_n", Pins("D8")),
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IOStandard("LVCMOS33")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 10.0
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, toolchain="vivado")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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