160 lines
7.2 KiB
Python
Executable File
160 lines
7.2 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Nathaniel Lewis <github@nrlewis.dev>
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.gen import *
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from litex.build.io import DDROutput
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from litex_boards.platforms import aliexpress_xc7k70t
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import *
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from litex.soc.cores.video import VideoS7HDMIPHY
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from litex.soc.cores.led import LedChaser
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from litedram.modules import W9812G6JB, SDRModule
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_hdmi = ClockDomain()
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self.cd_hdmi5x = ClockDomain()
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if sdram_rate == "1:2":
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_ps = ClockDomain()
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else:
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self.cd_sys_ps = ClockDomain()
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# Clk/Rst
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clk50 = platform.request("clk50")
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# PLL
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self.pll = pll = S7PLL()
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_hdmi, 25e6, margin=0)
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pll.create_clkout(self.cd_hdmi5x, 125e6, margin=0)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90)
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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# BaseSoC -----------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=100e6, sdram_rate="1:1",
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with_hdmi = False,
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with_ethernet = False,
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with_pcie = False,
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with_sdram = True,
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with_led_chaser = True,
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with_video_terminal = False,
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with_video_framebuffer = False,
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with_video_colorbars = False,
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**kwargs):
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platform = aliexpress_xc7k70t.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = CRG(platform, sys_clk_freq, sdram_rate)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alchitry Mojo", **kwargs)
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# Add SDRAM if a shield with RAM has been added
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if not self.integrated_main_ram_size:
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.crg.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = W9812G6JB(sys_clk_freq, sdram_rate),
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l2_cache_size = kwargs.get("l2_size", 1024)
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)
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# HDMI Options -----------------------------------------------------------------------------
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if with_hdmi and (with_video_colorbars or with_video_framebuffer or with_video_terminal):
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self.videophy = VideoS7HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi")
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if with_video_colorbars:
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self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet:
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self.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks", 0),
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pads = self.platform.request("eth", 0),
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tx_delay = 1.417e-9,
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rx_delay = 1.417e-9,
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)
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self.add_ethernet(phy=self.ethphy)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=aliexpress_xc7k70t.Platform, description="LiteX SoC on AliExpress XC7K70T PCIe board.")
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parser.add_target_argument("--sys-clk-freq", default=90e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate: (1:1 Full Rate or 1:2 Half Rate).")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable ethernet")
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parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe")
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parser.add_argument("--with-hdmi", action="store_true", help="Enable HDMI")
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viopts = parser.target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (HDMI).")
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args = parser.parse_args()
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# Note: baudrate is fixed because regardless of USB->TTL baud, the AVR <-> FPGA baudrate is
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# set to a fixed rate of 500 kilobaud.
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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sdram_rate = args.sdram_rate,
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with_ethernet = args.with_ethernet,
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with_pcie = args.with_pcie,
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with_hdmi = args.with_hdmi,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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with_video_colorbars = args.with_video_colorbars,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if __name__ == "__main__":
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main()
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