224 lines
9.0 KiB
Python
Executable File
224 lines
9.0 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) Greg Davill <greg.davill@gmail.com>
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# Copyright (c) Lone Dynamics Corporation <info@lonedynamics.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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import os
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import sys
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import json
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import machdyne_kopflos
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.build.io import DDROutput
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.soc.cores.clock import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.usb_ohci import USBOHCI
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.interconnect.csr_eventmanager import *
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from litedram.modules import MT41K64M16, MT41K128M16, MT41K256M16, MT41K512M16
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from litedram.phy import ECP5DDRPHY
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from litex.soc.integration.soc import SoCRegion
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# CRG ---------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, sdram_rate):
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self.rst = Signal()
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self.cd_por = ClockDomain()
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self.cd_sys = ClockDomain()
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_i = ClockDomain()
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self.cd_init = ClockDomain()
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self.stop = Signal()
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self.reset = Signal()
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# Clk / Rst
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clk48 = platform.request("clk48")
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk48)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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sys2x_clk_ecsout = Signal()
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self.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | self.rst)
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pll.register_clkin(clk48, 48e6)
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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pll.create_clkout(self.cd_init, 24e6)
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self.specials += [
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Instance("ECLKBRIDGECS",
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i_CLK0 = self.cd_sys2x_i.clk,
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i_SEL = 0,
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o_ECSOUT = sys2x_clk_ecsout),
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Instance("ECLKSYNCB",
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i_ECLKI = sys2x_clk_ecsout,
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i_STOP = self.stop,
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o_ECLKO = self.cd_sys2x.clk),
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Instance("CLKDIVF",
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p_DIV = "2.0",
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i_ALIGNWD = 0,
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i_CLKI = self.cd_sys2x.clk,
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i_RST = self.reset,
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o_CDIVX = self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
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]
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pll2 = ECP5PLL()
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self.pll2 = pll2
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pll2.register_clkin(clk48, 48e6)
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self.cd_usb_12 = ClockDomain()
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self.cd_usb = ClockDomain()
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self.cd_usb_48 = ClockDomain()
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self.cd_usb_48 = self.cd_usb
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pll2.create_clkout(self.cd_usb, 48e6)
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pll2.create_clkout(self.cd_usb_12, 12e6)
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self.comb += pll2.reset.eq(~por_done)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {**SoCCore.mem_map, **{
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"usb_ohci": 0xc0000000,
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}}
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def __init__(self, revision="v0", device="12F", sdram_device="MT41K128M16", sdram_rate="1:2", sys_clk_freq=int(50e6), toolchain="trellis", with_led_chaser=True, with_usb_host=False, with_ethernet=False, **kwargs):
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platform = machdyne_kopflos.Platform(revision=revision, device=device ,toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Schoko", **kwargs)
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# DDR3L ----------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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available_sdram_modules = {
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"MT41K64M16": MT41K64M16,
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"MT41K128M16": MT41K128M16,
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"MT41K256M16": MT41K256M16,
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"MT41K512M16": MT41K512M16,
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}
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sdram_module = available_sdram_modules.get(sdram_device)
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ddram_pads = platform.request("ddram")
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self.ddrphy = ECP5DDRPHY(
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pads = ddram_pads,
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sys_clk_freq = sys_clk_freq,
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cmd_delay = 0 if sys_clk_freq > 64e6 else 100)
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self.ddrphy.settings.rtt_nom = "disabled"
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = sdram_module(sys_clk_freq, "1:2"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# USB Host ---------------------------------------------------------------------------------
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if with_usb_host:
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self.usb_ohci = USBOHCI(platform, platform.request("usb_host"), usb_clk_freq=int(48e6))
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self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False))
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self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
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self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)
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if with_ethernet:
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from liteeth.phy.rmii import LiteEthPHYRMII
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self.ethphy = LiteEthPHYRMII(
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clock_pads = platform.request("eth_clocks"),
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pads = platform.request("eth"),
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with_hw_init_reset=True,
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refclk_cd=None)
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self.add_ethernet(phy=self.ethphy)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Schoko")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream to SRAM.")
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target_group.add_argument("--flash", action="store_true", help="Flash bitstream to MMOD.")
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target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
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target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
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target_group.add_argument("--revision", default="v0", help="Board Revision (v0).")
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target_group.add_argument("--device", default="12F", help="ECP5 device (12F, 25F, 45F or 85F).")
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target_group.add_argument("--cable", default="usb-blaster", help="Specify an openFPGALoader cable.")
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target_group.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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target_group.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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target_group.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.")
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target_group.add_argument("--with-ethernet", action="store_true", help="Enable ethernet support.")
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target_group.add_argument("--boot-from-flash", action="store_true", help="Boot from flash MMOD.")
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target_group.add_argument("--sdram-device", default="MT41K128M16", help="SDRAM device.")
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builder_args(parser)
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soc_core_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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toolchain = args.toolchain,
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revision = args.revision,
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device = args.device,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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sdram_device = args.sdram_device,
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with_usb_host = args.with_usb_host,
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with_ethernet = args.with_ethernet,
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**soc_core_argdict(args))
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if args.with_sdcard:
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soc.add_sdcard()
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
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if args.build:
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builder.build(**builder_kargs)
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if args.load:
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prog = soc.platform.create_programmer(args.cable)
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer(args.cable)
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prog.flash(0x100000, builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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