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__init__.py
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Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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2020-02-03 09:36:30 +01:00 |
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ac701.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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acorn_cle_215.py
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targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block.
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2020-11-12 12:08:20 +01:00 |
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aller.py
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targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block.
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2020-11-12 12:08:20 +01:00 |
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alveo_u250.py
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targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block.
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2020-11-12 12:08:20 +01:00 |
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arty.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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arty_s7.py
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target: add rst signal to CRG to allow full reset of the SoC on reboot command.
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2020-11-04 11:13:42 +01:00 |
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c10lprefkit.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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camlink_4k.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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colorlight_5a_75x.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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crosslink_nx_evn.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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crosslink_nx_vip.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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de0nano.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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de1soc.py
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target: add rst signal to CRG to allow full reset of the SoC on reboot command.
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2020-11-04 11:13:42 +01:00 |
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de2_115.py
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target: add rst signal to CRG to allow full reset of the SoC on reboot command.
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2020-11-04 11:13:42 +01:00 |
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de10lite.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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de10nano.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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ecp5_evn.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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ecpix5.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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fk33.py
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targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block.
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2020-11-12 12:08:20 +01:00 |
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fomu.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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genesys2.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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hadbadge.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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icebreaker.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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kc705.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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kcu105.py
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targets/Ultrascale: add missing AsyncResetSynchronizer import.
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2020-11-09 10:25:05 +01:00 |
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kx2.py
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target: add rst signal to CRG to allow full reset of the SoC on reboot command.
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2020-11-04 11:13:42 +01:00 |
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linsn_rv901t.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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logicbone.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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mercury_xu5.py
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targets/Ultrascale: add missing AsyncResetSynchronizer import.
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2020-11-09 10:25:05 +01:00 |
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mimas_a7.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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minispartan6.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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mist.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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nereid.py
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targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block.
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2020-11-12 12:08:20 +01:00 |
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netv2.py
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targets/netv2: add PCIe.
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2020-11-12 12:16:01 +01:00 |
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nexys4ddr.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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nexys_video.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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orangecrab.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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pano_logic_g2.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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pipistrello.py
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target: add rst signal to CRG to allow full reset of the SoC on reboot command.
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2020-11-04 11:13:42 +01:00 |
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simple.py
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targets/simple: simplify (only keep minimal SoC + Leds) and add load argument.
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2020-11-12 13:54:30 +01:00 |
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tagus.py
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targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block.
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2020-11-12 12:08:20 +01:00 |
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tec0117.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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trellisboard.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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ulx3s.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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vc707.py
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target: add rst signal to CRG to allow full reset of the SoC on reboot command.
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2020-11-04 11:13:42 +01:00 |
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vcu118.py
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targets/Ultrascale: add missing AsyncResetSynchronizer import.
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2020-11-09 10:25:05 +01:00 |
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versa_ecp5.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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xcu1525.py
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targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block.
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2020-11-12 12:08:20 +01:00 |
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zcu104.py
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targets/Ultrascale: add missing AsyncResetSynchronizer import.
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2020-11-09 10:25:05 +01:00 |
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zybo_z7.py
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target: add rst signal to CRG to allow full reset of the SoC on reboot command.
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2020-11-04 11:13:42 +01:00 |
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