177 lines
8.3 KiB
Python
177 lines
8.3 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Sergiu Mosanu <sm7ed@virginia.edu>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs -----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("sysclk", 0,
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Subsignal("n", Pins("BJ44"), IOStandard("LVDS")),
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Subsignal("p", Pins("BJ43"), IOStandard("LVDS")),
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),
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("sysclk", 1,
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Subsignal("n", Pins("BJ6"), IOStandard("LVDS")),
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Subsignal("p", Pins("BH6"), IOStandard("LVDS")),
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),
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("cpu_reset", 0, Pins("L30"), IOStandard("LVCMOS18")),
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# Leds
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("gpio_led", 0, Pins("C32"), IOStandard("LVCMOS18")),
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("gpio_led", 1, Pins("D32"), IOStandard("LVCMOS18")),
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("gpio_led", 2, Pins("D31"), IOStandard("LVCMOS18")),
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# Switches
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("gpio_sw", 0, Pins("J30"), IOStandard("LVCMOS18")),
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("gpio_sw", 1, Pins("J32"), IOStandard("LVCMOS18")),
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("gpio_sw", 2, Pins("K32"), IOStandard("LVCMOS18")),
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("gpio_sw", 3, Pins("K31"), IOStandard("LVCMOS18")),
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# Serial
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("serial", 0,
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Subsignal("rx", Pins("A28"), IOStandard("LVCMOS18")),
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Subsignal("tx", Pins("B33"), IOStandard("LVCMOS18")),
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),
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# DDR4 SDRAM
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#("ddram_reset_gate", 0, Pins(""), IOStandard("LVCMOS12")),???
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("ddram", 0,
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Subsignal("a", Pins(
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"BF46 BG43 BK45 BF42 BL45 BF43 BG42 BL43",
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"BK43 BM42 BG45 BD41 BL42 BE44"),
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IOStandard("SSTL12_DCI")),
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Subsignal("act_n", Pins("BH41"), IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("BH45 BM47"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("BF41 BE41"), IOStandard("SSTL12_DCI")),
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Subsignal("cas_n", Pins("BL46"), IOStandard("SSTL12_DCI")), # A15
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Subsignal("cke", Pins("BH42"), IOStandard("SSTL12_DCI")),
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Subsignal("clk_n", Pins("BJ46"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("clk_p", Pins("BH46"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("cs_n", Pins("BK46"), IOStandard("SSTL12_DCI")),
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Subsignal("dq", Pins(
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"BN32 BP32 BL30 BM30 BP29 BP28 BP31 BN31",
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"BJ31 BH31 BF32 BF33 BH29 BH30 BF31 BG32",
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"BK31 BL31 BK33 BL33 BL32 BM33 BN34 BP34",
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"BH34 BH35 BF35 BF36 BJ33 BJ34 BG34 BG35",
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"BM52 BL53 BL52 BL51 BN50 BN51 BN49 BM48",
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"BE50 BE49 BE51 BD51 BF52 BF51 BG50 BF50",
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"BH50 BJ51 BH51 BH49 BK50 BK51 BJ49 BJ48",
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"BN44 BN45 BM44 BM45 BP43 BP44 BN47 BP47"),
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IOStandard("POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_n", Pins(
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"BN30 BM29 BK30 BG30 BM35 BN35 BK35 BJ32",
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"BM50 BP49 BF48 BG49 BJ47 BK49 BP46 BP42"), #"BJ54 BJ53"
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IOStandard("DIFF_POD12"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_p", Pins(
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"BN29 BM28 BJ29 BG29 BL35 BM34 BK34 BH32",
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"BM49 BP48 BF47 BG48 BH47 BK48 BN46 BN42"), #"BH54 BJ52"
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IOStandard("DIFF_POD12"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("odt", Pins("BG44"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("BH44"), IOStandard("SSTL12_DCI")), # A16
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Subsignal("reset_n", Pins("BG33"), IOStandard("LVCMOS12")),
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Subsignal("we_n", Pins("BE43"), IOStandard("SSTL12_DCI")), # A14
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Misc("SLEW=FAST")
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),
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("ddram", 1,
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Subsignal("a", Pins(
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"BF7 BK1 BF6 BF5 BE3 BE6 BE5 BG7",
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"BJ1 BG2 BJ8 BE4 BL2 BK5"), # BK8 BJ4 BF8
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IOStandard("SSTL12_DCI")),
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Subsignal("act_n", Pins("BG3"), IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("BG8 BK4"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("BF3 BF2"), IOStandard("SSTL12_DCI")),
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Subsignal("cas_n", Pins("BJ4"), IOStandard("SSTL12_DCI")), # A15
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Subsignal("cke", Pins("BE1"), IOStandard("SSTL12_DCI")),
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Subsignal("clk_n", Pins("BJ2"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("clk_p", Pins("BJ3"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("cs_n", Pins("BL3"), IOStandard("SSTL12_DCI")),
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Subsignal("dq", Pins(
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"A11 A10 A9 A8 B12 B10 C12 B11",
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"E11 D11 E12 F11 F10 E9 F9 G11",
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"H12 G13 H13 H14 J11 J12 J15 J14",
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"A14 C15 A15 B15 F15 E14 F14 F13",
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"BM3 BM4 BM5 BL6 BN4 BN5 BN6 BN7",
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"BJ9 BK9 BK10 BL10 BM9 BN9 BN10 BM10",
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"BM15 BM14 BL15 BM13 BN12 BM12 BP13 BP14",
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"BJ13 BJ12 BH15 BH14 BK14 BK15 BL12 BL13"),
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IOStandard("POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_n", Pins(
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"A13 D9 G15 D14 BM7 BM8 BN14 BK13",
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"BF11 C9 G10 K13 D12 BP6 BP8 BP11"), # "BK11 BH9"
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IOStandard("DIFF_POD12"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_p", Pins(
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"B13 C10 D10 H10 H15 K14 D15 E13",
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"BL7 BP7 BL8 BP9 BN15 BP12 BJ14 BJ11"), #"BH54 BJ52"
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IOStandard("DIFF_POD12"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("odt", Pins("BH2"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("BF8"), IOStandard("SSTL12_DCI")), # A16
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Subsignal("reset_n", Pins("BH12"), IOStandard("LVCMOS12")),
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Subsignal("we_n", Pins("BK8"), IOStandard("SSTL12_DCI")), # A14
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Misc("SLEW=FAST")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = []
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "sysclk"
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default_clk_period = 1e9/100e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xcu280-fsvh2892-2L-e-es1", _io, _connectors, toolchain="vivado")
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("sysclk", 0, loose=True), 1e9/100e6)
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self.add_period_constraint(self.lookup_request("sysclk", 1, loose=True), 1e9/100e6)
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# For passively cooled boards, overheating is a significant risk if airflow isn't sufficient
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self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]")
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# Reduce programming time
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self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]")
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# DDR4 memory channel C0 Internal Vref
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 64]")
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]")
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]")
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# DDR4 memory channel C1 Internal Vref
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 68]")
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 69]")
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 70]")
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# Other suggested configurations
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self.add_platform_command("set_property CONFIG_VOLTAGE 1.8 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]")
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self.add_platform_command("set_property CONFIG_MODE SPIx4 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design]") |