214 lines
9.1 KiB
Python
Executable File
214 lines
9.1 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# Build/Use ----------------------------------------------------------------------------------------
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# Build/Load bitstream:
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# ./sqrl_acorn.py --uart-name=crossover --with-pcie --build --driver --load (or --flash)
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#
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#.Build the kernel and load it:
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# cd build/<platform>/driver/kernel
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# make
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# sudo ./init.sh
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#
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# Test userspace utilities:
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# cd build/<platform>/driver/user
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# make
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# ./litepcie_util info
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# ./litepcie_util scratch_test
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# ./litepcie_util dma_test
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# ./litepcie_util uart_test
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import os
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from migen import *
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from litex.gen import LiteXModule
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from litex_boards.platforms import sqrl_acorn
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.xadc import XADC
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from litex.soc.cores.dna import DNA
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from litedram.modules import MT41K512M16
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from litedram.phy import s7ddrphy
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_sys4x_dqs = ClockDomain()
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self.cd_idelay = ClockDomain()
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# Clk/Rst
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clk200 = platform.request("clk200")
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# PLL
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self.pll = pll = S7PLL()
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk200, 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC -----------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, variant="cle-215+", sys_clk_freq=int(100e6), with_led_chaser=True,
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with_pcie=False, with_sata=False, **kwargs):
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platform = sqrl_acorn.Platform(variant=variant)
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# CRG --------------------------------------------------------------------------------------
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self.crg = CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Acorn CLE-101/215(+)", **kwargs)
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# XADC -------------------------------------------------------------------------------------
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self.xadc = XADC()
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# DNA --------------------------------------------------------------------------------------
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self.dna = DNA()
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self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 200e6)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K512M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1, address_width=64)
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# FIXME: Apply it to all targets (integrate it in LitePCIe?).
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platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
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platform.toolchain.pre_placement_commands.add("set_clock_groups -group [get_clocks {sys_clk}] -group [get_clocks userclk2] -asynchronous", sys_clk=self.crg.cd_sys.clk)
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platform.toolchain.pre_placement_commands.add("set_clock_groups -group [get_clocks {sys_clk}] -group [get_clocks clk_125mhz] -asynchronous", sys_clk=self.crg.cd_sys.clk)
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platform.toolchain.pre_placement_commands.add("set_clock_groups -group [get_clocks {sys_clk}] -group [get_clocks clk_250mhz] -asynchronous", sys_clk=self.crg.cd_sys.clk)
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platform.toolchain.pre_placement_commands.add("set_clock_groups -group [get_clocks clk_125mhz] -group [get_clocks clk_250mhz] -asynchronous")
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# ICAP (For FPGA reload over PCIe).
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from litex.soc.cores.icap import ICAP
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self.icap = ICAP()
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self.icap.add_reload()
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self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
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# Flash (For SPIFlash update over PCIe).
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from litex.soc.cores.gpio import GPIOOut
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from litex.soc.cores.spi_flash import S7SPIFlash
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self.flash_cs_n = GPIOOut(platform.request("flash_cs_n"))
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self.flash = S7SPIFlash(platform.request("flash"), sys_clk_freq, 25e6)
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# SATA -------------------------------------------------------------------------------------
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if with_sata:
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from litex.build.generic_platform import Subsignal, Pins
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from litesata.phy import LiteSATAPHY
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# IOs
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_sata_io = [
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# PCIe 2 SATA Custom Adapter (With PCIe Riser / SATA cable mod).
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("pcie2sata", 0,
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Subsignal("tx_p", Pins("B6")),
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Subsignal("tx_n", Pins("A6")),
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Subsignal("rx_p", Pins("B10")),
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Subsignal("rx_n", Pins("A10")),
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),
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]
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platform.add_extension(_sata_io)
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# RefClk, Generate 150MHz from PLL.
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self.cd_sata_refclk = ClockDomain()
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self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
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sata_refclk = ClockSignal("sata_refclk")
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platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
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# PHY
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self.sata_phy = LiteSATAPHY(platform.device,
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refclk = sata_refclk,
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pads = platform.request("pcie2sata"),
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gen = "gen1",
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clk_freq = sys_clk_freq,
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data_width = 16)
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# Core
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self.add_sata(phy=self.sata_phy, mode="read+write")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=sqrl_acorn.Platform, description="LiteX SoC on Acorn CLE-101/215(+)")
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parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
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parser.add_target_argument("--variant", default="cle-215+", help="Board variant (cle-215+, cle-215 or cle-101).")
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parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
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pcieopts = parser.target_group.add_mutually_exclusive_group()
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pcieopts.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
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parser.add_target_argument("--driver", action="store_true", help="Generate PCIe driver.")
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parser.add_target_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support (requires SDCard adapter on P2).")
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pcieopts.add_argument("--with-sata", action="store_true", help="Enable SATA support (over PCIe2SATA).")
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args = parser.parse_args()
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soc = BaseSoC(
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variant = args.variant,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_pcie = args.with_pcie,
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with_sata = args.with_sata,
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**parser.soc_core_argdict
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)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, builder.get_bitstream_filename(mode="flash"))
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if __name__ == "__main__":
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main()
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