Florent Kermarrec 347b477b07 sipeed_tang_primer_20k: Fix DDR3 module, SoC reset and remove DDR3 debug code. ... Now passing memtest with valid reported memory size: __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2023 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS CRC passed (d32a9529) LiteX git sha1: 85dadb82 --=============== SoC ==================-- CPU: VexRiscv SMP-LINUX @ 48MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 64.0KiB SRAM: 6.0KiB L2: 512B SDRAM: 128.0MiB 16-bit @ 192MT/s (CL-6 CWL-5) MAIN-RAM: 128.0MiB --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Read leveling: m0, b00: |00000000| delays: - m0, b01: |00000000| delays: - m0, b02: |01100000| delays: 01+-00 m0, b03: |00000000| delays: - best: m0, b02 delays: 01+-00 m1, b00: |00000000| delays: - m1, b01: |00000000| delays: - m1, b02: |01100000| delays: 01+-00 m1, b03: |00000000| delays: - best: m1, b02 delays: 01+-00 Switching SDRAM to hardware control. Memtest at 0x40000000 (2.0MiB)... Write: 0x40000000-0x40200000 2.0MiB Read: 0x40000000-0x40200000 2.0MiB Memtest OK Memspeed at 0x40000000 (Sequential, 2.0MiB)... Write speed: 11.7MiB/s Read speed: 17.4MiB/s		2023-08-29 16:50:17 +02:00
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platforms	Merge pull request #515 from josuah/crosslink_nx_openocd	2023-08-28 16:35:20 +02:00
prog	platforms/crosslink_nx_evn: allow use of OpenOCD	2023-08-08 23:25:41 +02:00
targets	sipeed_tang_primer_20k: Fix DDR3 module, SoC reset and remove DDR3 debug code.	2023-08-29 16:50:17 +02:00
__init__.py	litex_boards: Remove short imports since not really longer useful and mess up Python imports.	2022-05-03 17:53:57 +02:00