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8211aca2e8
We initially wanted to provide different level of support for the platforms/targets, mainly to avoid too much maintenance and let each contributor update its contributed platforms and targets, but it's easier to update all platforms/targets all-together when LiteX evolves or changes (and that's what has been done on litex-boards since the creation of the repository). So let just simplify things and avoid this differentiation.
39 lines
1.4 KiB
Python
39 lines
1.4 KiB
Python
# This file is Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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# IOs ------------------------------------------------------------------
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_io = [
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("clk50", 0, Pins("AF14"), IOStandard("3.3-V LVTTL")),
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("serial", 0,
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Subsignal("tx", Pins("AC18"), IOStandard("3.3-V LVTTL")), # JP1 GPIO[0]
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Subsignal("rx", Pins("Y17"), IOStandard("3.3-V LVTTL")) # JP1 GPIO[1]
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),
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("sdram_clock", 0, Pins("AH12"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins("AK14 AH14 AG15 AE14 AB15 AC14 AD14 AF15 AH15 AG13 AG12 AH13 AJ14")),
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Subsignal("ba", Pins("AF13 AJ12")),
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Subsignal("cs_n", Pins("AG11")),
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Subsignal("cke", Pins("AK13")),
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Subsignal("ras_n", Pins("AE13")),
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Subsignal("cas_n", Pins("AF11")),
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Subsignal("we_n", Pins("AA13")),
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Subsignal("dq", Pins("AK6 AJ7 AK7 AK8 AK9 AG10 AK11 AJ11 AH10 AJ10 AJ9 AH9 AH8 AH7 AJ6 AJ5")),
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Subsignal("dm", Pins("AB13 AK12")),
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IOStandard("3.3-V LVTTL")
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),
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]
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# Platform -------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self):
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AlteraPlatform.__init__(self, "5CSEMA5F31C6", _io)
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