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376a836583
./sipeed_tang_nano_4k.py --cpu-type=vexriscv --cpu-variant=lite --build --flash __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2021 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Sep 17 2021 15:54:08 BIOS CRC passed (6cc6de6d) Migen git sha1: a5bc262 LiteX git sha1: 46cd9c5a --=============== SoC ==================-- CPU: VexRiscv_Lite @ 27MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 64KiB SRAM: 8KiB FLASH: 4096KiB --========== Initialization ============-- Initializing W25Q32 SPI Flash @0x80000000... SPI Flash clk configured to 13 MHz Memspeed at 0x80000000 (Sequential, 4.0KiB)... Read speed: 1.3MiB/s Memspeed at 0x80000000 (Random, 4.0KiB)... Read speed: 521.9KiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex>
108 lines
4 KiB
Python
Executable file
108 lines
4 KiB
Python
Executable file
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex_boards.platforms import tang_nano_4k
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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# Clk / Rst
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clk27 = platform.request("clk27")
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rst_n = platform.request("user_btn", 0)
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self.comb += self.cd_sys.clk.eq(clk27)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
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def __init__(self, sys_clk_freq=int(27e6), with_led_chaser=True, **kwargs):
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platform = tang_nano_4k.Platform()
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# Put BIOS in SPIFlash to save BlockRAMs.
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kwargs["integrated_rom_size"] = 0
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kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + 0
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Tang Nano 4K",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SPI Flash --------------------------------------------------------------------------------
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from litespi.modules import W25Q32
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=W25Q32(Codes.READ_1_1_1), with_master=False)
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.mem_map["spiflash"] + 0,
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size = 64*kB,
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linker = True)
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)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Tang Nano 4K")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--flash", action="store_true", help="Flash Bitstream")
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parser.add_argument("--sys-clk-freq",default=27e6, help="System clock frequency (default: 27MHz)")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"))
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prog.flash(0, "build/sipeed_tang_nano_4k/software/bios/bios.bin", external=True)
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if __name__ == "__main__":
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main()
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