201 lines
8.7 KiB
Python
Executable File
201 lines
8.7 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 Arnaud Durand <arnaud.durand@unifr.ch>
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# Copyright (c) 2022 Martin Hubacek @hubmartin (Twitter)
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# Copyright (c) 2022 Raptor Engineering, LLC
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import versa_ecp5
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex_boards.platforms import rcs_arctic_tern_bmc_card
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.soc import SoCRegion
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from litedram.modules import MT41J256M16
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from litedram.phy import ECP5DDRPHY
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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from litex.soc.cores.video import VideoGenericPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_init = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys2x_eb = ClockDomain(reset_less=True)
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self.clock_domains.cd_dvo = ClockDomain(reset_less=True)
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# # #
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self.stop = Signal()
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self.reset = Signal()
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# Clk / Rst
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clk125 = platform.request("clk125")
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rst_n = platform.request("rst_n")
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self.clk_inv_alignwd = Signal()
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self.sys_inv_clk_bridge = Signal()
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self.sys_inv_clk_syncb = Signal()
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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sys2x_clk_ecsout = Signal()
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst)
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pll.register_clkin(clk125, 125e6)
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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pll.create_clkout(self.cd_init, 24e6)
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self.specials += [
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Instance("OSCG",
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p_DIV = 128, # 2.4MHz
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o_OSC = self.cd_por.clk),
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Instance("ECLKBRIDGECS",
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i_CLK0 = self.cd_sys2x_i.clk,
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i_SEL = 0,
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o_ECSOUT = sys2x_clk_ecsout),
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Instance("ECLKSYNCB",
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i_ECLKI = sys2x_clk_ecsout,
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i_STOP = self.stop,
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o_ECLKO = self.cd_sys2x.clk),
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Instance("CLKDIVF",
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p_DIV = "2.0",
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i_ALIGNWD = 0,
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i_CLKI = self.cd_sys2x.clk,
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i_RST = self.reset,
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o_CDIVX = self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
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AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset),
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]
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# Generate DVO clock
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pll.create_clkout(self.cd_dvo, 40e6) # 800x600@60
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#pll.create_clkout(self.cd_dvo, 148.35e6) # 1920x1080@60
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#pll.create_clkout(self.cd_dvo, 148.2e6) # 1920x1200@60
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), toolchain="trellis",
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with_video_colorbars = False,
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with_video_terminal = True,
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with_video_framebuffer = False,
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with_ethernet = False,
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with_etherbone = False,
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eth_ip = "192.168.1.50",
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**kwargs):
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platform = rcs_arctic_tern_bmc_card.Platform(toolchain=toolchain)
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#bios_flash_offset = 0x400000
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# Set CPU variant / reset address
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#kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
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kwargs["integrated_rom_size"] = 0x10000
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, irq_n_irqs=16, clk_freq=sys_clk_freq,
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ident = "LiteX SoC on Arctic Tern (BMC card carrier)",
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#integrated_main_ram_size = 0x40000,
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#integrated_main_ram_size = 0,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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self.submodules.ddrphy = ECP5DDRPHY(
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platform.request("ddram"),
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sys_clk_freq=sys_clk_freq)
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J256M16(sys_clk_freq, "1:2"), # Not MT41J256M16, but the AS4C256M16D3C in use has similar specifications
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l2_cache_size = kwargs.get("l2_size", 8192),
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks", 0),
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pads = self.platform.request("eth", 0),
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tx_delay = 0e-9,
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rx_delay = 0e-9)
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# Video Output -----------------------------------------------------------------------------
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if with_video_colorbars or with_video_terminal or with_video_framebuffer:
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dvo_pads = platform.request("dvo")
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self.submodules.videophy = VideoGenericPHY(dvo_pads, clock_domain="dvo", with_clk_ddr_output=False)
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if with_video_terminal:
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#self.add_video_terminal(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="dvo")
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#self.add_video_terminal(phy=self.videophy, timings="1920x1200@60Hz", clock_domain="dvo")
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="dvo")
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elif with_video_framebuffer:
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#self.add_video_framebuffer(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="dvo")
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#self.add_video_framebuffer(phy=self.videophy, timings="1920x1200@60Hz", clock_domain="dvo")
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self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="dvo")
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else:
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self.add_video_colorbars(phy=self.videophy, timings="800x600@60Hz", clock_domain="dvo")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Arctic Tern (BMC card carrier)")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond")
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parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)")
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ethopts = parser.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
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builder_args(parser)
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soc_core_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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toolchain = args.toolchain,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
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if __name__ == "__main__":
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main()
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