245 lines
9.4 KiB
Python
245 lines
9.4 KiB
Python
#!/usr/bin/env python3
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# This file is Copyright (c) 2019 Sean Cross <sean@xobs.io>
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# This file is Copyright (c) 2018 David Shah <dave@ds0.me>
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# This file is Copyright (c) 2020 Piotr Esden-Tempski <piotr@esden.net>
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# License: BSD
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# This target was originally based on the Fomu target.
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.soc.cores import up5kspram, spi_flash
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.integration.builder import Builder, builder_argdict, builder_args
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from litex.soc.integration.soc_core import soc_core_argdict, soc_core_args
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from litex.soc.integration.doc import AutoDoc
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from litex.soc.integration.common import SoCMemRegion
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from litex_boards.partner.platforms.icebreaker import Platform
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.uart import UARTWishboneBridge
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import litex.soc.cores.cpu
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import os, shutil, subprocess
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class JumpToAddressROM(wishbone.SRAM):
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def __init__(self, size, addr):
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data = [
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0x00000537 | ((addr & 0xfffff000) << 0), # lui a0,%hi(addr)
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0x00052503 | ((addr & 0x00000fff) << 20), # lw a0,%lo(addr)(a0)
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0x000500e7, # jalr a0
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]
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wishbone.SRAM.__init__(self, size, read_only=True, init=data)
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module, AutoDoc):
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"""Icebreaker Clock Resource Generator
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The following clock domains are available on this design:
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+---------+------------+---------------------------------+
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| Name | Frequency | Description |
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+=========+============+=================================+
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+---------+------------+---------------------------------+
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| clk_12 | 12 MHz | Main control logic |
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+---------+------------+---------------------------------+
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| sys | 12 MHz | System CPU and wishbone bus |
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+---------+------------+---------------------------------+
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"""
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def __init__(self, platform):
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clk12 = platform.request("clk12")
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reset_delay = Signal(12, reset=4095)
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self.clock_domains.cd_por = ClockDomain()
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self.reset = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_clk_12 = ClockDomain()
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platform.add_period_constraint(self.cd_sys.clk, 1e9 / 12e6)
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platform.add_period_constraint(self.cd_clk_12.clk, 1e9 / 12e6)
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# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# reset.
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self.comb += [
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self.cd_por.clk.eq(self.cd_sys.clk),
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self.cd_sys.rst.eq(reset_delay != 0),
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self.cd_clk_12.rst.eq(reset_delay != 0),
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]
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self.comb += self.cd_sys.clk.eq(clk12)
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self.comb += self.cd_clk_12.clk.eq(clk12)
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self.sync.por += \
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If(reset_delay != 0,
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reset_delay.eq(reset_delay - 1))
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self.specials += AsyncResetSynchronizer(self.cd_por, self.reset)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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"""A SoC on iCEBreaker, optionally with a softcore CPU"""
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# Statically-define the memory map, to prevent it from shifting across
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# various litex versions.
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SoCCore.mem_map = {
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"rom": 0x00000000, # (default shadow @0x80000000)
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"sram": 0x10000000, # (default shadow @0xa0000000)
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"spiflash": 0x20000000, # (default shadow @0xa0000000)
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"csr": 0xe0000000, # (default shadow @0x60000000)
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"vexriscv_debug": 0xf00f0000,
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}
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def __init__(self, pnr_placer="heap", pnr_seed=0, debug=True,
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boot_vector=0x2001a000,
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**kwargs):
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"""Create a basic SoC for iCEBraker.
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Create a basic SoC for iCEBraker. The `sys` frequency will run at 12 MHz.
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Args:
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pnr_placer (str): Which placer to use in nextpnr
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pnr_seed (int): Which seed to use in nextpnr
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Returns:
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Newly-constructed SoC
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"""
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platform = Platform()
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if "cpu_type" not in kwargs:
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kwargs["cpu_type"] = None
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kwargs["cpu_variant"] = None
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else:
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kwargs["cpu_reset_address"] = boot_vector
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clk_freq = int(12e6)
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# Force the SRAM size to 0, because we add our own SRAM with SPRAM
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kwargs["integrated_sram_size"] = 0
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kwargs["integrated_rom_size"] = 0
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if debug:
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kwargs["uart_name"] = "crossover"
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if kwargs["cpu_type"] == "vexriscv":
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kwargs["cpu_variant"] = kwargs["cpu_variant"] + "+debug"
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SoCCore.__init__(self, platform, clk_freq,
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with_uart=True,
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with_ctrl=True,
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**kwargs)
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# If there is a VexRiscv CPU, add a fake ROM that simply tells the CPU
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# to jump to the given address.
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if hasattr(self, "cpu") and self.cpu.name == "vexriscv":
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self.add_memory_region("rom", 0, 16)
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self.submodules.rom = JumpToAddressROM(16, boot_vector)
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self.submodules.crg = _CRG(platform)
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# UP5K has single port RAM, which is a dedicated 128 kilobyte block.
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# Use this as CPU RAM.
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spram_size = 128 * 1024
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self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
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self.register_mem("sram", self.mem_map["sram"], self.spram.bus, spram_size)
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# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
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# for doing writes.
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spi_pads = platform.request("spiflash4x")
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self.submodules.lxspi = spi_flash.SpiFlash(spi_pads, dummy=6, endianness="little")
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self.register_mem("spiflash", self.mem_map["spiflash"], self.lxspi.bus, size=16 * 1024 * 1024)
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self.add_csr("lxspi")
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# In debug mode, add a UART bridge. This takes over from the normal UART bridge,
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# however you can use the "crossover" UART to communicate with this over the bridge.
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if debug:
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self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
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self.add_wb_master(self.uart_bridge.wishbone)
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if hasattr(self, "cpu") and self.cpu.name == "vexriscv":
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self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100)
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# Override default LiteX's yosys/build templates
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assert hasattr(platform.toolchain, "yosys_template")
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assert hasattr(platform.toolchain, "build_template")
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platform.toolchain.yosys_template = [
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"{read_files}",
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"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
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"synth_ice40 -json {build_name}.json -top {build_name}",
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]
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platform.toolchain.build_template = [
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"yosys -q -l {build_name}.rpt {build_name}.ys",
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"nextpnr-ice40 --json {build_name}.json --pcf {build_name}.pcf --asc {build_name}.txt \
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--pre-pack {build_name}_pre_pack.py --{architecture} --package {package}",
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"icepack {build_name}.txt {build_name}.bin"
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]
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# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
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# The "-reult" adds an additional LUT pass to pack more stuff in,
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# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
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# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
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# This increases density, and lets us use the FPGA more efficiently.
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platform.toolchain.yosys_template[2] += " -relut -abc2 -dffe_min_ce_use 4 -relut"
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# if use_dsp:
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# platform.toolchain.yosys_template[2] += " -dsp"
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# Disable final deep-sleep power down so firmware words are loaded
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# onto softcore's address bus.
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platform.toolchain.build_template[2] = "icepack -s {build_name}.txt {build_name}.bin"
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# Allow us to set the nextpnr seed
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platform.toolchain.build_template[1] += " --seed " + str(pnr_seed)
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if pnr_placer is not None:
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platform.toolchain.build_template[1] += " --placer {}".format(pnr_placer)
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self.mem_regions["rom"] = SoCMemRegion(0x2001a000, 16 * 1024 * 1024 - 0x1a000, "cached")
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self.mem_regions["boot"] = SoCMemRegion(0, 16, "cached")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
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parser.add_argument(
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"--seed", default=0, help="seed to use in nextpnr"
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)
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parser.add_argument(
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"--placer", default="heap", choices=["sa", "heap"], help="which placer to use in nextpnr"
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)
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parser.add_argument(
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"--cpu", action="store_true", help="Add a CPU to the build"
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)
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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kwargs = builder_argdict(args)
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if args.cpu:
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kwargs["cpu_type"] = "vexriscv"
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kwargs["cpu_variant"] = "min"
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soc = BaseSoC(pnr_placer=args.placer, pnr_seed=args.seed,
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debug=True, **kwargs)
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kwargs = builder_argdict(args)
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# Don't build software -- we don't include it since we just jump
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# to SPI flash.
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kwargs["compile_software"] = True
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builder = Builder(soc, **kwargs)
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builder.build()
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if __name__ == "__main__":
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main()
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