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47 lines
1.5 KiB
Python
47 lines
1.5 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Ilia Sergachev <ilia.sergachev@protonmail.ch>
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk50", 0, Pins("L19"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("rx", Pins("B20"), IOStandard("LVCMOS33")),
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Subsignal("tx", Pins("A19"), IOStandard("LVCMOS33")),
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),
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# Buttons
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("user_btn", 0, Pins("M19"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("M20"), IOStandard("LVCMOS33")),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = []
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/506
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def __init__(self, toolchain="trellis", **kwargs):
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LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381I", _io, _connectors, toolchain=toolchain, **kwargs)
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def create_programmer(self):
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return OpenFPGALoader("ecpix5")
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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