Florent Kermarrec 3df677cfeb Add initial Analog Pocket platform/target with Clk/SDRAM, able to run a simple SoC with SDRAM over JTAG-UART. ... $ ./analog_pocket.py --uart-name=jtag_uart --build --load $ litex_term jtag --jtag-config=openocd_usb_blaster.cfg __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2023 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Sep 21 2023 08:53:57 BIOS CRC passed (1e2b3f44) LiteX git sha1: 7d738737 --=============== SoC ==================-- CPU: VexRiscv @ 50MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 128.0KiB SRAM: 8.0KiB L2: 8.0KiB SDRAM: 64.0MiB 16-bit @ 50MT/s (CL-2 CWL-2) MAIN-RAM: 64.0MiB --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Switching SDRAM to hardware control. Memtest at 0x40000000 (2.0MiB)... Write: 0x40000000-0x40200000 2.0MiB Read: 0x40000000-0x40200000 2.0MiB Memtest OK Memspeed at 0x40000000 (Sequential, 2.0MiB)... Write speed: 15.6MiB/s Read speed: 22.1MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex>		2023-09-21 09:19:57 +02:00
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platforms	Add initial Analog Pocket platform/target with Clk/SDRAM, able to run a simple SoC with SDRAM over JTAG-UART.	2023-09-21 09:19:57 +02:00
prog	prog: Remove too specific openocd_max10_blaster/2.cfg.	2023-09-21 09:17:00 +02:00
targets	Add initial Analog Pocket platform/target with Clk/SDRAM, able to run a simple SoC with SDRAM over JTAG-UART.	2023-09-21 09:19:57 +02:00
__init__.py	litex_boards: Remove short imports since not really longer useful and mess up Python imports.	2022-05-03 17:53:57 +02:00