121 lines
5.4 KiB
Python
121 lines
5.4 KiB
Python
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020-2021 Xuanyu Hu <xuanyu.hu@whu.edu.cn>
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# SPDX-License-Identifier: BSD-2-Clause
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# ported by Alex Petrov aka sysman
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# Kintex7-420T aliexpress
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# Part xc7k420tiffg901-2L v0.2
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from migen import *
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from litex_boards.platforms import u420t
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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# board is grade 2, but to fix halts use -1
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self.submodules.pll = pll = S7MMCM(speedgrade=-2)
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##self.submodules.pll = pll = S7MMCM(speedgrade=-1)
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self.comb += pll.reset.eq(~platform.request("user_btn_k3") | self.rst)
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pll.register_clkin(platform.request("clk100"), 100e6)
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#workaround to bypass for clk100 error: No nets matched 'clk100'
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#line:940 litex/litex/build/xilinx/vivado.py " [get_ports {clk}]", clk=clk)
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## platform.add_platform_command("create_clock -name clk100 -period 10.0 [get_ports clk100]")
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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# platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk100]")
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# Reduce programming time
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#self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]")
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_spi_flash=False, **kwargs):
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platform = u420t.Platform()
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# --- add more sram for riscv comfort
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# xc7k420t BRAMs: 1670 (col length: RAMB18 160 RAMB36 80)
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kwargs["integrated_rom_size"] = 0x8000 # 8kb
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kwargs["integrated_sram_size"] = 0x10000 # 64kb
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kwargs["integrated_main_ram_size"] = 0x40000 # 256kb ## change if needed
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# SoCCore ----------------------------------_-----------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on u420t",
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Video ------------------------------------------------------------------------------------
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# no video
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# no ram
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import N25Q256
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x", module=W25Q256(Codes.READ_1_1_4))
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Add ROM linker region --------------------------------------------------------------------
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#self.bus.add_region("rom", SoCRegion(
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# origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
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# size = 32*kB,
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# linker = True)
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#)
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#self.cpu.set_reset_address(self.bus.regions["rom"].origin)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on u420t")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
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# sdopts = target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-flash", action="store_true", help="Enable SPI-mode flash support.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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# soc.platform.add_extension(u420t._sdcard_pmod_io)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(obuilder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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